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  1. Aug 23, 2015
    • Marek Vasut's avatar
      arm: socfpga: Move wrappers into platform directory · ca62d2e1
      Marek Vasut authored
      
      Move the wrappers for QTS-generated files into platform directory
      out of the board directory. The trick here is to add -I to CFLAGS
      such that it points to the board directory in source tree and thus
      the qts/ directory there is still reachable.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      ca62d2e1
    • Marek Vasut's avatar
      arm: socfpga: Do not enable gmac1 in Cyclone V dtsi · c2624240
      Marek Vasut authored
      
      The GMAC which is enabled is purely board property, so do not enable
      arbitrary GMAC in DT include files. Same goes for PHY mode, which is
      again a board property. The CycloneV SoCDK does this correctly, but
      SoCrates doesn't. This bug never manifested itself though, since all
      the boards ever used the GMAC1 . This bug manifests itself only on
      boards that utilise GMAC0.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      c2624240
    • Marek Vasut's avatar
      arm: socfpga: Make the DT mmc node consistent · afe13993
      Marek Vasut authored
      
      The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
      This makes aliases not very usable, so make everything into mmc0.
      Moreover, zap the useless mmc alias while at this.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      afe13993
    • Marek Vasut's avatar
      arm: socfpga: Fix delay in clock manager · 7e4d2fa2
      Marek Vasut authored
      
      This code claims it needs to wait 7us, yet it uses get_timer() function
      which operates with millisecond granularity. Use timer_get_us() instead,
      which operates with microsecond granularity.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      7e4d2fa2
    • Marek Vasut's avatar
      arm: socfpga: Fix delay in freeze controller · a8535c30
      Marek Vasut authored
      
      Based on observation, this udelay(20) was apparently too high and caused
      subsequent failure to calibrate DDR when U-Boot was compiled with certain
      toolchains. Lowering this delay fixed the problem.
      
      Instead of permanently lowering the delay, calculate the correct delay
      based on the original comment, that is, obtain EOSC1 frequency and use
      it to calculate the precise delay.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      a8535c30
    • Marek Vasut's avatar
      ddr: altera: Repair uninited variable · 35e47b71
      Marek Vasut authored
      
      Fix the following problem:
      drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
      drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized]
        if (found_passing_read && found_failing_read)
                               ^
      drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here
        u32 found_passing_read, found_failing_read, initial_failing_dtap;
                                ^
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      35e47b71
    • Marek Vasut's avatar
      ddr: altera: Replace float multiplication with integer one · 6d7a3330
      Marek Vasut authored
      
      This gem is really really rare, there was an actual float used in
      the Altera DDR init code, which pulled in floating point ops from
      the libgcc, just wow.
      
      Since we don't support floating point operations the same way Linux
      does not support them, replace this with an integer multiplication
      and division combo. This removes some 2kiB of size from the SPL as
      the floating point ops are no longer pulled in from libgcc.
      
      This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which
      does not contain the floating point bits.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      6d7a3330
  2. Aug 20, 2015
  3. Aug 19, 2015
  4. Aug 18, 2015
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