- Oct 07, 2016
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Add device tree node for Ricoh RN5T567. Currently we do not need the individual DC/DC converters or LDO's (and they are also not yet supported by the driver). Signed-off-by:Stefan Agner <stefan.agner@toradex.com>
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Add device model enabled PMIC driver for Ricoh RN5T567 PMIC used on Colibri iMX7. Signed-off-by:
Simon Glass <sjg@chromium.org>
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We now use device tree to provide SoC data to the UART driver, there is no need for the legancy UART platform data. Signed-off-by: -
Remove legancy I2C config and code in favor of upcomming DM/DT enable I2C support. Signed-off-by: -
Add base device for NXP i.MX 7Solo/7Dual. The two SoC are very similar and hence can share the same device tree for boot loaders purpose. Signed-off-by:
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Add pinctrl defines for NXP i.MX 7Solo/7Dual SoC. The pinctrl format is compatible to the Linux kernel, hence this file is a simple copy from the Linux kernel (commit 97f5c1817b7e). Signed-off-by: -
It is not usual that drivers announce when they have been initialized. use dev_dbg to announce device initialization. Signed-off-by:
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Support instatiation through device tree. Also parse the fsl,dte-mode property to determine whether DTE mode shall be used. Signed-off-by:
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- Oct 06, 2016
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Add a README file to explain how to build and flash the SD card for Udoo boards. Signed-off-by:Fabio Estevam <fabio.estevam@nxp.com>
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Signed-off-by:Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
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PCM052 SoMs may be equipped with various sizes of DDR. Keep default of 256MB; new PCM052-based targets will specify their actual DDR size. Linux command line is auto-adjusted to DDR size. Signed-off-by: -
This format can be flashed directly at address 0 of the NAND FLASH, as it contains all necessary headers. Signed-off-by: -
Add the 'm4go' command to pcm052-based targets. It loads scatter file images. Signed-off-by: -
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Merge 'spare' into 'bootloader' partition Use same partition for ramdisk and rootfs boot scenarios. Remove 'ramdisk' partition, use 'rootfs' for ramdisk (ramdisk and nand boot scenarios are mutually exclusive). Expand last partition to end of actual NAND size. Adjust UBIFS rootfs boot kernel arguments. Signed-off-by:
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- Oct 04, 2016
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>From TO1.1, SNVS adds internal pull up control for POR_B, the register filed is GPBIT[1:0], after system boot up, it can be set to 2b'01 to disable internal pull up. It can save about 30uA power in SNVS mode. Signed-off-by:Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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For i.MX6, the mux width is 4, not 3. So enlarge the width. IOMUX_CONFIG_LPSR is changed from 0x8 to 0x20 to not use bit 3 of mux. Signed-off-by: -
Currently the bmode "usb" uses BOOT_CFG1 to 0x01, -which means BOOT_CFG1[7:4] is set to b0000. According to Table 8-7 Boot Device Selection this is NOR/OneNAND and not Reserved. Use 0x10 which leads to b0001, which is a Reserved boot device. With that the SoC reliably falls back to the serial loader. Cc: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by:
Troy Kisky <troy.kisky@boundarydevices.com>
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Add i.MX6ULL EVK board support: Add device tree file, which is copied from NXP Linux. Enabled DM_MMC, DM_GPIO, DM_I2C, DM_SPI, PINCTRL, DM_REGULATOR. The uart iomux settings are still keeped in board file. Boot Log: U-Boot 2016.09-rc1-00366-gbb419ef-dirty (Aug 11 2016 - 13:08:58 +0800) CPU: Freescale i.MX6ULL rev1.0 at 396MHz CPU: Commercial temperature grade (0C to 95C) at 15C Reset cause: POR Model: Freescale i.MX6 ULL 14x14 EVK Board Board: MX6ULL 14x14 EVK DRAM: 512 MiB MMC: initialized IMX pinctrl driver FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 => mmc dev 1 switch to partitions #0, OK mmc1 is current device Signed-off-by: -
Need to initialize mmc->dev when probe, or will met "dev_get_uclass_priv: null device", when `mmc dev 1`. Signed-off-by:
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Add device tree for i.MX6ULL. Signed-off-by: -
Add i.mx6ul clock header, copied from kernel commit (29b4817d401). i.MX6ULL reuse the file in Linux Kernel, so let's keep the same. Signed-off-by: -
Add pinctrl defines for NXP i.MX 6ULL. Since i.MX6ULL reuses some definitions of i.MX6UL, also add i.MX6UL pinctrl defines from linux kernel commit (29b4817d401). Signed-off-by: -
There two iomuxc for i.MX6ULL. one iomuxc is compatible is i.MX6UL, the other iomuxc is for SVNS usage, similar with the one in mx7. Signed-off-by: -
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Signed-off-by: -
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by:
Bai Ping <ping.bai@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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Since the mx6ull adds the AIPS3, so enable its initialization. Signed-off-by:
Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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Update memory map address for mx6ull. Signed-off-by:
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Update Clock settings and CCM register map for i.MX6ULL. Signed-off-by:
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Adjust POR_B settings on i.MX6ULL according to IC design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by:
Anson Huang <Anson.Huang@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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Update misc SOC related settings for i.MX6ULL, such as FEC mac address, cpu speed grading and mmdc channel mask clearing. Also update s_init to skip pfd reset. Signed-off-by: -
Since MX6ULL select MX6UL, we can not use IS_ENABLED(CONFIG_MX6UL) here, because this piece code is only for i.MX6UL. Signed-off-by:
Stefano Babic <sbabic@denx.de>
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Rom already initialized clock at 396M and 132M for arm core and ahb, so skip setting them again in U-Boot. Signed-off-by:
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The i.MX6ULL's GPT supportting taking OSC as clock source. Add i.MX6ULL support. Signed-off-by:
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i.MX6ULL has two 128 bits fuse banks, bank 7 and bank 8, while other banks use 256 bits. So we have to adjust the word and bank index when accessing the bank 8. When in command line `fuse read 8 0 1`, you can image `fuse read 7 4 1` in the ocotp driver implementation for 6ULL. When programming, we use word index, so need to fix bank7/8 programming for i.mx6ull. For example: fuse prog 8 3 1; The word index is (8 << 3 | 3) --> 67. But actully it should be (7 << 3 | 7) ---> 63. So fix it. Signed-off-by: -
Introduce is_mx6ull macro. Signed-off-by: -
i.MX6ULL is derivative from i.MX6UL, so select MX6UL for MX6ULL. If need to differenate MX6ULL from MX6UL, use CONFIG_MX6ULL Signed-off-by:
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Add i.MX6ULL major cpu type. Signed-off-by:
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Add iomux header file for i.MX6ULL. Signed-off-by:
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Correct name is "Boundary Devices". Signed-off-by:
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