- Jan 09, 2008
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Marcel Ziswiler authored
Signed-off-by:
Marcel Ziswiler <marcel@ziswiler.com>
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Marcel Ziswiler authored
Signed-off-by:
Marcel Ziswiler <marcel@ziswiler.com>
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- Jan 04, 2008
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Stefan Roese authored
The Sequoia NAND booting target now uses the recently extracted cpu/ppc4xx/denali_data_eye.c file too. Signed-off-by:
Stefan Roese <sr@denx.de>
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- Dec 28, 2007
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Stefan Roese authored
Use correct link to nand_ecc now located in drivers/mtd/nand/ for the platforms mentioned above. Signed-off-by:
Stefan Roese <sr@denx.de>
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- Nov 25, 2007
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- Nov 03, 2007
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Stefan Roese authored
This patch adds NAND booting support for the AMCC 405EX(r) eval boards. Again, only one image supports both targets. Signed-off-by:
Stefan Roese <sr@denx.de>
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- Oct 31, 2007
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Stefan Roese authored
Since the cache handling functions were moved from start.S into cache.S the acadia NAND booting Makfile needs to be adapted accordingly. Signed-off-by:
Stefan Roese <sr@denx.de>
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Eugene O'Brien authored
This patch also adds a note to the fixed DDR setup for Bamboo NAND booting: Note: As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM modules are still plugged in. So it is recommended to remove the DIMM modules while using the NAND booting code with the fixed SDRAM setup! Signed-off-by:
Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by:
Stefan Roese <sr@denx.de>
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- Sep 11, 2007
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Grzegorz Bernacki authored
Bamboo has a file sdram.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by:
Grzegorz Bernacki <gjb@semihalf.com>
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- Jun 19, 2007
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Stefan Roese authored
The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by:
Stefan Roese <sr@denx.de>
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- Jun 06, 2007
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Stefan Roese authored
This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by:
Stefan Roese <sr@denx.de>
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- Jun 01, 2007
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Stefan Roese authored
Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
The U-Boot NAND booting support is now extended to support ECC upon loading of the NAND U-Boot image. Tested on AMCC Sequoia (440EPx) and Bamboo (440EP). Signed-off-by:
Stefan Roese <sr@denx.de>
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- May 05, 2007
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Stefan Roese authored
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by:
Stefan Roese <sr@denx.de>
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- Mar 06, 2007
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Stefan Roese authored
As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by:
Stefan Roese <sr@denx.de>
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- Jan 05, 2007
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Stefan Roese authored
This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by:
Stefan Roese <sr@denx.de>
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- Oct 23, 2006
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Marian Balakowicz authored
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- Oct 08, 2006
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Wolfgang Denk authored
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- Sep 12, 2006
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Stefan Roese authored
Patch by Stefan Roese, 12 Sep 2006
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Stefan Roese authored
Patch by Stefan Roese, 12 Sep 2006
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- Sep 07, 2006
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Stefan Roese authored
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
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