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  • Florian Mayer Florian Mayer fmayer
1 author
  1. Sep 05, 2008
    • Adam Graham's avatar
      ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines · f6b6c458
      Adam Graham authored 
      
Signed-off-by: default avatarAdam Graham <agraham@amcc.com>
Signed-off-by: default avatarStefan Roese <sr@denx.de>
      f6b6c458
    • Adam Graham's avatar
      ppc4xx: IBM Memory Controller DDR autocalibration routines · 075d0b81
      Adam Graham authored 
      
Alternate SDRAM DDR autocalibration routine that can be generically used
for any PPC4xx chips that have the IBM SDRAM Controller core allowing for
support of more DIMM/memory chip vendors and gets the DDR autocalibration
values which give the best read latency performance (SDRAM0_RDCC.[RDSS]).

Two alternate SDRAM DDR autocalibration algoritm are provided in this patch,
"Method_A" and "Method_B".  DDR autocalibration Method_A scans the full range
of possible PPC4xx  SDRAM Controller DDR autocalibration values and takes a
lot longer to run than Method_B.  Method_B executes in the same amount of time
as the currently existing DDR autocalibration routine, i.e. 1 second or so.
Normally Method_B is used and it is set as the default method.

The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM
Controller registers.[bit-field]:
1)  SDRAM0_RQDC.[RQFD]
2)  SDRAM0_RFDC.[RFFD]

This alternate PPC4xx DDR autocalibration code calibrates the following
IBM SDRAM Controller registers.[bit-field]:

1)  SDRAM0_WRDTR.[WDTR]
2)  SDRAM0_CLKTR.[CKTR]
3)  SDRAM0_RQDC.[RQFD]
4)  SDRAM0_RFDC.[RFFD]

and will also use the calibrated settings of the above four registers that
produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS]
register.[bit-field].

Signed-off-by: default avatarAdam Graham <agraham@amcc.com>
Signed-off-by: default avatarStefan Roese <sr@denx.de>
      075d0b81
    • Ricardo Ribalda's avatar
      ppc44x: Unification of virtex5 pp440 boards · e07f4a80
      Ricardo Ribalda authored 
      
This patch provides an unificated way of handling xilinx v5 ppc440 boards.

It unificates 3 different things:

1) Source code
A new board called ppc440-generic has been created. This board includes
a generic tlb initialization (Maps the whole memory into virtual) and
defines board_pre_init, checkboard, initdram and get_sys_info weakly,
so, they can be replaced by specific functions.

If a new board needs to redefine any of the previous functions
(specific initialization) it can create a new directory with the
specific initializations needed. (see the example ml507 board).

2) Configuration file
Common configurations are located under configs/xilinx-ppc440.h, this
header file interpretes the xparameters file generated by EDK and
configurates u-boot in correspondence. Example: if there is a Temac,
allows CMD_CONFIG_NET
Specific configuration are located under specific configuration file.
(see the example ml507 board)

3) Makefile
Some work has been done in order to not duplicate work in the Main
Makefile. Please see the attached code.

In order to support new boards they can be implemented in the next way:

a) Simple Generic Board  (90% of the time)
Using EDK generates a new xparameters.h file, replace
ppc440-generic/xparameters.h  and run make xilinx-ppc440-generic_config
&& make

b) Simple Boards with special u-boot parameters (9 % of the time)
Create a new file under configs for it (use ml507.h as example) and
change your paramaters. Create a new Makefile paragraph and compile

c) Complex boards (1% of the time)
Create a new folder for the board, like the ml507

Finally, it adds support for the Avnet FX30T Evaluation board, following
the new generic structure:

Cheap board by Avnet for evaluating the Virtex5 FX technology.

This patch adds support for:
 - UartLite
 - 16MB Flash
 - 64MB RAM

Prior using U-boot in this board, read carefully the ERRATA by Avnet
to solve some memory initialization issues.

Signed-off-by: default avatarRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: default avatarStefan Roese <sr@denx.de>
      e07f4a80
  3. Sep 03, 2008