In order to configure the PMIC at an early stage, we add the driver
for SPL. The registers to set are taken from the NXP EVK in
downstream uboot-imx. We only do the configuration that might be
essential for booting the kernel. We will let the kernel driver
handle all the advanced settings for voltage scaling in suspend mode,
etc.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Igor Opaniuk authored 4 years ago and Frieder Schrempf committed 4 years ago

Add SPL_DM_PMIC_PCA9450 symbol to Kconfig.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

Max Krummenacher authored 4 years ago and Frieder Schrempf committed 4 years ago

The I2C address is 0x25, not 0x35. This according to the datasheet and
tests with a PCA9450A.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

Sébastien Szymanski authored 4 years ago and Frieder Schrempf committed 4 years ago

Quoting Ye Li from NXP:

    "We have confirmed with PMIC team, 0x35 is used only on early chips
    and not used any more. 0x25 is the final address."

Fix it by merging power_pca9450a_init and power_pca9450b_init into one
function power_pca9450_init.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

Ye Li authored 5 years ago and Frieder Schrempf committed 4 years ago

PCA9450 PMIC series is used to support iMX8MM (PCA9450A) and
iMX8MN (PCA9450B). Add the PMIC driver for both PCA9450A and PCA9450B.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Similar as in bc9b2bd1 for the display detection, we are using
the wrong I2C port for detecting the old PMIC in order to print the
deprecation warning.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

mx8mm/spl.c in function do_board_detect: scan on i2c bus 1 for address 0x5d (goodix touchcontroller)

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

If less than 8G is available on the board, we detect it at
runtime.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

We backported support for a common dram_init() in the soc.c file.
Let's use it.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

If we want to detect DDR sizes up to 8G at runtime, we need to set
PHYS_SDRAM_SIZE and PHYS_SDRAM_2_SIZE to their maximums of 3G and
5G respectively. In case there is actually only 4G of RAM available,
we need to calculate the correct sizes for bank 1 and 2.

This method works if board_phys_sdram_size() is defined to return
the actual RAM size accross both banks by calling get_ram_size().

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Tim Harvey authored 4 years ago and Frieder Schrempf committed 4 years ago

the mem_map structure containing the size of SDRAM is used in various
cache functions in cache_v8.c thus we need to update it with the
sdram size the board is configured with as well. Without this
the cache functions do not get setup properly and can hang
in the case where a board reports more SDRAM than defined in
PHYS_SDRAM_SIZE.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Peng Fan authored 4 years ago and Frieder Schrempf committed 4 years ago

Current codes assume the OPTEE address is at the end of first DRAM bank.
Adjust the process to allow OPTEE in the middle of first bank.

When OPTEE memory is removed from first bank, it may split the first bank
to two banks, adjust the MMU table for the split case,
Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge
i.MX8MP evk to default to avoid issue.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Tested-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

The preferred property to pass the MAC address to the kernel is
local-mac-address. Only use mac-address as a fallback.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

For rev0 of the SoM we had a very small batch with a 2GB RAM from some vendor.
We don't produce these anymore and now use DDR from Micron with 1/2/4GB. As
it makes things easier drop support for the old DDR and add support for the
4GB type instead.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

With the current devicetrees from Linux ethernet didn't work for some
reason. Disable the second ethernet and let the first one control MDIO
to make it work in U-Boot.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Jacky Bai authored 5 years ago and Frieder Schrempf committed 4 years ago

The 'selfref_en' should be bit'0', so correct the setting to
enable the auto self-refresh.

Reviewed-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

Oliver Chen authored 4 years ago and Frieder Schrempf committed 4 years ago

Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue

Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
[Backport to v2020.01-ktn]
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

On some SoMs we have a 2GB Micron RAM chip. Update the parameters
to be able to detect it correctly.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Change the message about the board type printed by SPL to match
what we have for i.MX8MM.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

This simplifies and cleans the configuration for the Kontron i.MX8MM
SoMs and boards. We adjust the devicetrees to reflect the changes
that were made in the kernel.

We also drop the support for the outdated rev0 boards.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Adam Ford authored 4 years ago and Frieder Schrempf committed 4 years ago

This patch synchronizes the device tree with that from 5.6.7.

This also adds nodes for crypto and ddrc, which makes keeping
the device tree files from individual boards in sync with the
Linux kernel.  This is helpful when boads reference those nodes.

Signed-off-by: Adam Ford <aford173@gmail.com>

Yoshio Furuyama authored 4 years ago and Frieder Schrempf committed 4 years ago

Add support for new Kioxia products.
The new Kioxia products support program load x4 command, and have
HOLD_D bit which is equivalent to QE bit.

Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com


Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Yoshio Furuyama authored 4 years ago and Frieder Schrempf committed 4 years ago

The suffix was changed from "G" to "J" to classify between 1st generation
and 2nd generation serial NAND devices (which now belong to the Kioxia
brand).
As reference that's
1st generation device of 1Gbit product is "TC58CVG0S3HRAIG"
2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ".

The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and
the prefix was changed from "TC58" to "TH58".

Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*().

Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com


Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Robert Marko authored 5 years ago and Frieder Schrempf committed 4 years ago

Toshiba recently launched new revisions of their serial SLC NAND series.
TC58CVG2S0HRAIJ is a refresh of previous series with minor improvements.
Basic parameters are same so lets add support for this new revision.

Datasheet: https://business.kioxia.com/info/docget.jsp?did=58601&prodName=TC58CVG2S0HRAIJ



Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Tested-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Otavio Salvador authored 4 years ago and Frieder Schrempf committed 4 years ago

The default boot fuse settings use the SD card (MMC1) as primary boot
device, but allow SPI NOR as a fallback boot device. We cannot use the
SPI NOR as primary boot otherwise we may mix the SPL (from the MMC1) and
U-Boot proper from the SPI NOR. Also if no U-Boot image is flashed to
SPI NOR, the boot will be interrupted as the SPI NOR access is
blocking the second boot device (MMC).

If booting for MMC we should use the U-Boot proper from MMC as first
try and SPI NOR only second.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
[Adjust comment/commit message and refactor code]
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

This reverts commit 3d58441a.

We can't always use the SPI NOR as first boot device, as this breaks
the case when we boot from SD-card and the SPI NOR boot is tried
first and blocking the other boot devices.

This is probably the case because there's currently no way to detect
if the SPI NOR is available (can be probed), but doesn't have
valid bootable content flashed!?

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

The default boot fuse settings use the SD card (MMC1) as primary
boot device, but allow SPI NOR as a fallback boot device.
We can't detect the fallback case and spl_boot_device() will return
BOOT_DEVICE_MMC1 despite the actual boot device beeing SPI NOR.
Therefore we provide a custom boot order to probe the SPI NOR first.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Otavio Salvador authored 4 years ago and Frieder Schrempf committed 4 years ago

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Otavio Salvador authored 4 years ago and Frieder Schrempf committed 4 years ago

We need to use BUS 1 during SPL as it still does not use the driver
model for using the device alias.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Otavio Salvador authored 4 years ago and Frieder Schrempf committed 4 years ago

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Peter Robinson authored 5 years ago and Frieder Schrempf committed 4 years ago

Same as the upstream fix for building dtc with gcc 10.

Upstream-Status: Backport [2020.04]

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
(cherry picked from commit 018921ee)

Otavio Salvador authored 4 years ago and Frieder Schrempf committed 4 years ago

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Otavio Salvador authored 4 years ago and Frieder Schrempf committed 4 years ago

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

Otavio Salvador authored 4 years ago and Frieder Schrempf committed 4 years ago

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>

This reverts commit 9531bfb9.