ddr: stm32mp1_ddr: correctly PWR DDR retention bits

If the DDR is not in self-refresh, the PWR DDR retention bits should be
cleared, whatever the status of PWR_CR3_DDRRETEN. This can happen in case
of STANDBY with DDR of, if the DDR has not been set in Self Refresh.

Change-Id: If8854b06ad4d2a8d0bf6e227c411efcdcd4b004a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/188935


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>

drivers/st/ddr/stm32mp1_ddr.c

@@ -815,14 +815,12 @@ void stm32mp1_ddr_init(struct ddr_info *priv,
 			VERBOSE("self-refresh aborted: no retention\n");
 			config->self_refresh = false;
 		}
-	} else {
-		if (ddr_reten != 0U) {
-			VERBOSE("disable DDR PHY retention\n");
-			mmio_setbits_32((uint32_t)(priv->pwr) + PWR_CR3,
-					PWR_CR3_DDRSRDIS);
-			mmio_clrbits_32((uint32_t)(priv->pwr) + PWR_CR3,
-					PWR_CR3_DDRRETEN);
-		}
+	}
+
+	if (!config->self_refresh) {
+		VERBOSE("disable DDR PHY retention\n");
+		mmio_setbits_32((uint32_t)(priv->pwr) + PWR_CR3, PWR_CR3_DDRSRDIS);
+		mmio_clrbits_32((uint32_t)(priv->pwr) + PWR_CR3, PWR_CR3_DDRRETEN);
 	}
 
 	/* DDR INIT SEQUENCE */