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Commit 59a1cdf1 authored by Yann Gautier's avatar Yann Gautier
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stm32mp1: update platform files 


Move print_reset_reason function to bl2_plat_setup.c
Put __unused attribute for unused bl2_el3_early_platform_setup args.
Rename dt_dev_info to dt_uart_info.
Put MMU configuration earlier.
Remove unused macros.
Use U() or ULL() macros where needed.
Use device tree to configure GIC.
Use GIC helper function.

Change-Id: I34620c421cc6967a668bca318f7689fd74fa78a6
Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
Signed-off-by: default avatarLionel Debieve <lionel.debieve@st.com>
parent 4156d4da
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with 245 additions and 204 deletions
plat/st/stm32mp1/bl2_io_storage.c
+ 36
− 90
View file @ 59a1cdf1
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -58,13 +58,26 @@ static const io_block_dev_spec_t mmc_block_dev_spec = { ...@@ -58,13 +58,26 @@ static const io_block_dev_spec_t mmc_block_dev_spec = {
static uintptr_t storage_dev_handle; static uintptr_t storage_dev_handle;
static const io_dev_connector_t *mmc_dev_con; static const io_dev_connector_t *mmc_dev_con;
#define IMG_IDX_BL33 0 static const io_block_spec_t bl32_block_spec = {
.offset = BL32_BASE,
.length = STM32MP1_BL32_SIZE
};
static const io_block_spec_t bl2_block_spec = {
.offset = BL2_BASE,
.length = STM32MP1_BL2_SIZE,
};
static const struct stm32image_part_info bl33_partition_spec = { static const struct stm32image_part_info bl33_partition_spec = {
.name = BL33_IMAGE_NAME, .name = BL33_IMAGE_NAME,
.binary_type = BL33_BINARY_TYPE, .binary_type = BL33_BINARY_TYPE,
}; };
enum {
IMG_IDX_BL33,
IMG_IDX_NUM
};
static struct stm32image_device_info stm32image_dev_info_spec = { static struct stm32image_device_info stm32image_dev_info_spec = {
.lba_size = MMC_BLOCK_SIZE, .lba_size = MMC_BLOCK_SIZE,
.part_info[IMG_IDX_BL33] = { .part_info[IMG_IDX_BL33] = {
...@@ -73,19 +86,12 @@ static struct stm32image_device_info stm32image_dev_info_spec = { ...@@ -73,19 +86,12 @@ static struct stm32image_device_info stm32image_dev_info_spec = {
}, },
}; };
static io_block_spec_t stm32image_block_spec; static io_block_spec_t stm32image_block_spec = {
.offset = 0,
static const io_dev_connector_t *stm32image_dev_con; .length = 0,
static const io_block_spec_t bl32_block_spec = {
.offset = BL32_BASE,
.length = STM32MP1_BL32_SIZE
}; };
static const io_block_spec_t bl2_block_spec = { static const io_dev_connector_t *stm32image_dev_con;
.offset = BL2_BASE,
.length = STM32MP1_BL2_SIZE,
};
static int open_dummy(const uintptr_t spec); static int open_dummy(const uintptr_t spec);
static int open_image(const uintptr_t spec); static int open_image(const uintptr_t spec);
...@@ -160,83 +166,18 @@ static void print_boot_device(boot_api_context_t *boot_context) ...@@ -160,83 +166,18 @@ static void print_boot_device(boot_api_context_t *boot_context)
} }
} }
static void print_reset_reason(void)
{
uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
if (rstsr == 0U) {
WARN("Reset reason unknown\n");
return;
}
INFO("Reset reason (0x%x):\n", rstsr);
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
INFO("System exits from STANDBY\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
INFO("MPU exits from CSTANDBY\n");
return;
}
}
if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
INFO(" Power-on Reset (rst_por)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
INFO(" Brownout Reset (rst_bor)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
INFO(" System reset generated by MPU (MPSYSRST)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
INFO(" Reset due to a clock failure on HSE\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
INFO(" IWDG1 Reset (rst_iwdg1)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
INFO(" IWDG2 Reset (rst_iwdg2)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" Pad Reset from NRST\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
INFO(" Reset due to a failure of VDD_CORE\n");
return;
}
ERROR(" Unidentified reset reason\n");
}
void stm32mp1_io_setup(void) void stm32mp1_io_setup(void)
{ {
int io_result __unused; int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
struct stm32_sdmmc2_params params; struct stm32_sdmmc2_params params;
struct mmc_device_info device_info; struct mmc_device_info device_info;
uintptr_t mmc_default_instance; uintptr_t mmc_default_instance;
const partition_entry_t *entry;
boot_api_context_t *boot_context = boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp1_get_boot_ctx_address(); (boot_api_context_t *)stm32mp1_get_boot_ctx_address();
print_reset_reason();
print_boot_device(boot_context); print_boot_device(boot_context);
if ((boot_context->boot_partition_used_toboot == 1U) || if ((boot_context->boot_partition_used_toboot == 1U) ||
...@@ -255,7 +196,7 @@ void stm32mp1_io_setup(void) ...@@ -255,7 +196,7 @@ void stm32mp1_io_setup(void)
switch (boot_context->boot_interface_selected) { switch (boot_context->boot_interface_selected) {
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
dmb(); dmbsy();
memset(&params, 0, sizeof(struct stm32_sdmmc2_params)); memset(&params, 0, sizeof(struct stm32_sdmmc2_params));
...@@ -309,14 +250,19 @@ void stm32mp1_io_setup(void) ...@@ -309,14 +250,19 @@ void stm32mp1_io_setup(void)
stm32image_dev_info_spec.device_size = stm32image_dev_info_spec.device_size =
stm32_sdmmc2_mmc_get_device_size(); stm32_sdmmc2_mmc_get_device_size();
stm32image_dev_info_spec.part_info[IMG_IDX_BL33].part_offset =
get_partition_entry(BL33_IMAGE_NAME)->start; for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
stm32image_dev_info_spec.part_info[IMG_IDX_BL33].bkp_offset = part = &stm32image_dev_info_spec.part_info[idx];
get_partition_entry(BL33_IMAGE_NAME)->length; entry = get_partition_entry(part->name);
if (entry == NULL) {
stm32image_block_spec.offset = 0; ERROR("Partition %s not found\n",
stm32image_block_spec.length = part->name);
get_partition_entry(BL33_IMAGE_NAME)->length; panic();
}
part->part_offset = entry->start;
part->bkp_offset = 0U;
}
/* /*
* Re-open MMC with io_mmc, for better perfs compared to * Re-open MMC with io_mmc, for better perfs compared to
......
plat/st/stm32mp1/bl2_plat_setup.c
+ 128
− 33
View file @ 59a1cdf1
...@@ -33,8 +33,95 @@ ...@@ -33,8 +33,95 @@
static struct console_stm32 console; static struct console_stm32 console;
void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, static void print_reset_reason(void)
u_register_t arg2, u_register_t arg3) {
uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
if (rstsr == 0U) {
WARN("Reset reason unknown\n");
return;
}
INFO("Reset reason (0x%x):\n", rstsr);
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
INFO("System exits from STANDBY\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
INFO("MPU exits from CSTANDBY\n");
return;
}
}
if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
INFO(" Power-on Reset (rst_por)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
INFO(" Brownout Reset (rst_bor)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" System reset generated by MCU (MCSYSRST)\n");
} else {
INFO(" Local reset generated by MCU (MCSYSRST)\n");
}
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
INFO(" System reset generated by MPU (MPSYSRST)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
INFO(" Reset due to a clock failure on HSE\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
INFO(" IWDG1 Reset (rst_iwdg1)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
INFO(" IWDG2 Reset (rst_iwdg2)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
INFO(" MPU Processor 0 Reset\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
INFO(" MPU Processor 1 Reset\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" Pad Reset from NRST\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
INFO(" Reset due to a failure of VDD_CORE\n");
return;
}
ERROR(" Unidentified reset reason\n");
}
void bl2_el3_early_platform_setup(u_register_t arg0,
u_register_t arg1 __unused,
u_register_t arg2 __unused,
u_register_t arg3 __unused)
{ {
stm32mp1_save_boot_ctx_address(arg0); stm32mp1_save_boot_ctx_address(arg0);
} }
...@@ -59,12 +146,38 @@ void bl2_platform_setup(void) ...@@ -59,12 +146,38 @@ void bl2_platform_setup(void)
void bl2_el3_plat_arch_setup(void) void bl2_el3_plat_arch_setup(void)
{ {
int32_t result; int32_t result;
struct dt_node_info dt_dev_info; struct dt_node_info dt_uart_info;
const char *board_model; const char *board_model;
boot_api_context_t *boot_context = boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp1_get_boot_ctx_address(); (boot_api_context_t *)stm32mp1_get_boot_ctx_address();
uint32_t clk_rate; uint32_t clk_rate;
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
/* Prevent corruption of preloaded BL32 */
mmap_add_region(BL32_BASE, BL32_BASE,
BL32_LIMIT - BL32_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
/* Map non secure DDR for BL33 load and DDR training area restore */
mmap_add_region(STM32MP1_DDR_BASE,
STM32MP1_DDR_BASE,
STM32MP1_DDR_MAX_SIZE,
MT_MEMORY | MT_RW | MT_NS);
/* Prevent corruption of preloaded Device Tree */
mmap_add_region(DTB_BASE, DTB_BASE,
DTB_LIMIT - DTB_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
configure_mmu();
if (dt_open_and_check() < 0) {
panic();
}
/* /*
* Disable the backup domain write protection. * Disable the backup domain write protection.
* The protection is enable at each reset by hardware * The protection is enable at each reset by hardware
...@@ -88,28 +201,8 @@ void bl2_el3_plat_arch_setup(void) ...@@ -88,28 +201,8 @@ void bl2_el3_plat_arch_setup(void)
mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
} }
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
/* Prevent corruption of preloaded BL32 */
mmap_add_region(BL32_BASE, BL32_BASE,
BL32_LIMIT - BL32_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
/* Prevent corruption of preloaded Device Tree */
mmap_add_region(DTB_BASE, DTB_BASE,
DTB_LIMIT - DTB_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
configure_mmu();
generic_delay_timer_init(); generic_delay_timer_init();
if (dt_open_and_check() < 0) {
panic();
}
if (stm32mp1_clk_probe() < 0) { if (stm32mp1_clk_probe() < 0) {
panic(); panic();
} }
...@@ -118,12 +211,12 @@ void bl2_el3_plat_arch_setup(void) ...@@ -118,12 +211,12 @@ void bl2_el3_plat_arch_setup(void)
panic(); panic();
} }
result = dt_get_stdout_uart_info(&dt_dev_info); result = dt_get_stdout_uart_info(&dt_uart_info);
if ((result <= 0) || if ((result <= 0) ||
(dt_dev_info.status == 0U) || (dt_uart_info.status == 0U) ||
(dt_dev_info.clock < 0) || (dt_uart_info.clock < 0) ||
(dt_dev_info.reset < 0)) { (dt_uart_info.reset < 0)) {
goto skip_console_init; goto skip_console_init;
} }
...@@ -131,25 +224,25 @@ void bl2_el3_plat_arch_setup(void) ...@@ -131,25 +224,25 @@ void bl2_el3_plat_arch_setup(void)
goto skip_console_init; goto skip_console_init;
} }
if (stm32mp1_clk_enable((unsigned long)dt_dev_info.clock) != 0) { if (stm32mp1_clk_enable((unsigned long)dt_uart_info.clock) != 0) {
goto skip_console_init; goto skip_console_init;
} }
stm32mp1_reset_assert((uint32_t)dt_dev_info.reset); stm32mp1_reset_assert((uint32_t)dt_uart_info.reset);
udelay(2); udelay(2);
stm32mp1_reset_deassert((uint32_t)dt_dev_info.reset); stm32mp1_reset_deassert((uint32_t)dt_uart_info.reset);
mdelay(1); mdelay(1);
clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock); clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_uart_info.clock);
if (console_stm32_register(dt_dev_info.base, clk_rate, if (console_stm32_register(dt_uart_info.base, clk_rate,
STM32MP1_UART_BAUDRATE, &console) == 0) { STM32MP1_UART_BAUDRATE, &console) == 0) {
panic(); panic();
} }
board_model = dt_get_board_model(); board_model = dt_get_board_model();
if (board_model != NULL) { if (board_model != NULL) {
NOTICE("%s\n", board_model); NOTICE("Model: %s\n", board_model);
} }
skip_console_init: skip_console_init:
...@@ -162,5 +255,7 @@ skip_console_init: ...@@ -162,5 +255,7 @@ skip_console_init:
stm32mp1_arch_security_setup(); stm32mp1_arch_security_setup();
print_reset_reason();
stm32mp1_io_setup(); stm32mp1_io_setup();
} }
plat/st/stm32mp1/include/platform_def.h
+ 7
− 10
View file @ 59a1cdf1
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -30,8 +30,8 @@ ...@@ -30,8 +30,8 @@
#define BL33_BINARY_TYPE U(0x0) #define BL33_BINARY_TYPE U(0x0)
#define STM32MP1_PRIMARY_CPU U(0x0) #define STM32MP1_PRIMARY_CPU U(0x0)
#define STM32MP1_SECONDARY_CPU U(0x1)
#define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT ULL(1) #define PLATFORM_CLUSTER_COUNT ULL(1)
#define PLATFORM_CLUSTER0_CORE_COUNT U(2) #define PLATFORM_CLUSTER0_CORE_COUNT U(2)
#define PLATFORM_CLUSTER1_CORE_COUNT U(0) #define PLATFORM_CLUSTER1_CORE_COUNT U(0)
...@@ -39,9 +39,9 @@ ...@@ -39,9 +39,9 @@
PLATFORM_CLUSTER0_CORE_COUNT) PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER 2 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2
#define MAX_IO_DEVICES 4 #define MAX_IO_DEVICES U(4)
#define MAX_IO_HANDLES 4 #define MAX_IO_HANDLES U(4)
#define MAX_IO_BLOCK_DEVICES 1 #define MAX_IO_BLOCK_DEVICES U(1)
/******************************************************************************* /*******************************************************************************
* BL2 specific defines. * BL2 specific defines.
...@@ -81,8 +81,8 @@ ...@@ -81,8 +81,8 @@
/******************************************************************************* /*******************************************************************************
* Platform specific page table and MMU setup constants * Platform specific page table and MMU setup constants
******************************************************************************/ ******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
/******************************************************************************* /*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is * Declarations and constants to access the mailboxes safely. Each mailbox is
...@@ -123,9 +123,6 @@ ...@@ -123,9 +123,6 @@
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
GIC_HIGHEST_SEC_PRIORITY, \ GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_LEVEL), \ grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(STM32MP1_IRQ_TAMPSERRS, \
GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \
GIC_HIGHEST_SEC_PRIORITY, \ GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_LEVEL), \ grp, GIC_INTR_CFG_LEVEL), \
......
plat/st/stm32mp1/platform.mk
+ 5
− 5
View file @ 59a1cdf1
...@@ -24,8 +24,8 @@ $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) ...@@ -24,8 +24,8 @@ $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
PLAT_INCLUDES := -Iplat/st/stm32mp1/include/ PLAT_INCLUDES := -Iplat/st/stm32mp1/include/
# Device tree # Device tree
STM32_DTB_FILE_NAME ?= stm32mp157c-ev1.dtb DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32_DTB_FILE_NAME))) FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME)))
DTC_FLAGS += -Wno-unit_address_vs_reg DTC_FLAGS += -Wno-unit_address_vs_reg
include lib/libfdt/libfdt.mk include lib/libfdt/libfdt.mk
...@@ -82,13 +82,13 @@ BL2_SOURCES += common/desc_image_load.c \ ...@@ -82,13 +82,13 @@ BL2_SOURCES += common/desc_image_load.c \
# Macros and rules to build TF binary # Macros and rules to build TF binary
STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed
STM32_DT_BASENAME := $(STM32_DTB_FILE_NAME:.dtb=) STM32_DT_BASENAME := $(DTB_FILE_NAME:.dtb=)
STM32_TF_STM32 := ${BUILD_PLAT}/tf-a-${STM32_DT_BASENAME}.stm32 STM32_TF_STM32 := ${BUILD_PLAT}/tf-a-${STM32_DT_BASENAME}.stm32
STM32_TF_BINARY := $(STM32_TF_STM32:.stm32=.bin) STM32_TF_BINARY := $(STM32_TF_STM32:.stm32=.bin)
STM32_TF_MAPFILE := $(STM32_TF_STM32:.stm32=.map) STM32_TF_MAPFILE := $(STM32_TF_STM32:.stm32=.map)
STM32_TF_LINKERFILE := $(STM32_TF_STM32:.stm32=.ld) STM32_TF_LINKERFILE := $(STM32_TF_STM32:.stm32=.ld)
STM32_TF_ELF := $(STM32_TF_STM32:.stm32=.elf) STM32_TF_ELF := $(STM32_TF_STM32:.stm32=.elf)
STM32_TF_DTBFILE := ${BUILD_PLAT}/fdts/${STM32_DTB_FILE_NAME} STM32_TF_DTBFILE := ${BUILD_PLAT}/fdts/${DTB_FILE_NAME}
STM32_TF_OBJS := ${BUILD_PLAT}/stm32mp1.o STM32_TF_OBJS := ${BUILD_PLAT}/stm32mp1.o
# Variables for use with stm32image # Variables for use with stm32image
...@@ -131,7 +131,7 @@ ${STM32_TF_OBJS}: plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP} ${STM32_TF_DTBFILE ...@@ -131,7 +131,7 @@ ${STM32_TF_OBJS}: plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP} ${STM32_TF_DTBFILE
-DDTB_BIN_PATH=\"${STM32_TF_DTBFILE}\" \ -DDTB_BIN_PATH=\"${STM32_TF_DTBFILE}\" \
-c plat/st/stm32mp1/stm32mp1.S -o $@ -c plat/st/stm32mp1/stm32mp1.S -o $@
${STM32_TF_LINKERFILE}: plat/st/stm32mp1/stm32mp1.ld.S ${STM32_TF_LINKERFILE}: plat/st/stm32mp1/stm32mp1.ld.S ${BUILD_PLAT}
@echo " LDS $<" @echo " LDS $<"
${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} -P -E $< -o $@ ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} -P -E $< -o $@
......
plat/st/stm32mp1/sp_min/sp_min_setup.c
+ 8
− 7
View file @ 59a1cdf1
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h> #include <common/debug.h>
#include <context.h> #include <context.h>
#include <drivers/arm/gicv2.h>
#include <drivers/arm/tzc400.h> #include <drivers/arm/tzc400.h>
#include <drivers/generic_delay_timer.h> #include <drivers/generic_delay_timer.h>
#include <drivers/st/stm32_console.h> #include <drivers/st/stm32_console.h>
...@@ -40,7 +41,7 @@ static struct console_stm32 console; ...@@ -40,7 +41,7 @@ static struct console_stm32 console;
******************************************************************************/ ******************************************************************************/
void sp_min_plat_fiq_handler(uint32_t id) void sp_min_plat_fiq_handler(uint32_t id)
{ {
switch (id) { switch (id & INT_ID_MASK) {
case STM32MP1_IRQ_TZC400: case STM32MP1_IRQ_TZC400:
ERROR("STM32MP1_IRQ_TZC400 generated\n"); ERROR("STM32MP1_IRQ_TZC400 generated\n");
panic(); panic();
...@@ -50,7 +51,7 @@ void sp_min_plat_fiq_handler(uint32_t id) ...@@ -50,7 +51,7 @@ void sp_min_plat_fiq_handler(uint32_t id)
panic(); panic();
break; break;
default: default:
ERROR("SECURE IT handler not define for it : %i", id); ERROR("SECURE IT handler not define for it : %u", id);
break; break;
} }
} }
...@@ -80,7 +81,7 @@ entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) ...@@ -80,7 +81,7 @@ entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3) u_register_t arg2, u_register_t arg3)
{ {
struct dt_node_info dt_dev_info; struct dt_node_info dt_uart_info;
int result; int result;
bl_params_t *params_from_bl2 = (bl_params_t *)arg0; bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
...@@ -114,10 +115,10 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, ...@@ -114,10 +115,10 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
panic(); panic();
} }
result = dt_get_stdout_uart_info(&dt_dev_info); result = dt_get_stdout_uart_info(&dt_uart_info);
if ((result > 0) && dt_dev_info.status) { if ((result > 0) && dt_uart_info.status) {
if (console_stm32_register(dt_dev_info.base, 0, if (console_stm32_register(dt_uart_info.base, 0,
STM32MP1_UART_BAUDRATE, &console) == STM32MP1_UART_BAUDRATE, &console) ==
0) { 0) {
panic(); panic();
......
plat/st/stm32mp1/stm32mp1_common.c
+ 1
− 17
View file @ 59a1cdf1
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -39,26 +39,11 @@ ...@@ -39,26 +39,11 @@
MT_SECURE | \ MT_SECURE | \
MT_EXECUTE_NEVER) MT_EXECUTE_NEVER)
#define MAP_DDR MAP_REGION_FLAT(STM32MP1_DDR_BASE, \
STM32MP1_DDR_MAX_SIZE, \
MT_MEMORY | \
MT_RW | \
MT_SECURE | \
MT_EXECUTE_NEVER)
#define MAP_DDR_NS MAP_REGION_FLAT(STM32MP1_DDR_BASE, \
STM32MP1_DDR_MAX_SIZE, \
MT_MEMORY | \
MT_RW | \
MT_NS | \
MT_EXECUTE_NEVER)
#if defined(IMAGE_BL2) #if defined(IMAGE_BL2)
static const mmap_region_t stm32mp1_mmap[] = { static const mmap_region_t stm32mp1_mmap[] = {
MAP_SRAM, MAP_SRAM,
MAP_DEVICE1, MAP_DEVICE1,
MAP_DEVICE2, MAP_DEVICE2,
MAP_DDR,
{0} {0}
}; };
#endif #endif
...@@ -67,7 +52,6 @@ static const mmap_region_t stm32mp1_mmap[] = { ...@@ -67,7 +52,6 @@ static const mmap_region_t stm32mp1_mmap[] = {
MAP_SRAM, MAP_SRAM,
MAP_DEVICE1, MAP_DEVICE1,
MAP_DEVICE2, MAP_DEVICE2,
MAP_DDR_NS,
{0} {0}
}; };
#endif #endif
......
plat/st/stm32mp1/stm32mp1_def.h
+ 2
− 13
View file @ 59a1cdf1
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -125,14 +125,6 @@ enum ddr_type { ...@@ -125,14 +125,6 @@ enum ddr_type {
#define STM32MP1_DEBUG_USART_BASE UART4_BASE #define STM32MP1_DEBUG_USART_BASE UART4_BASE
#define STM32MP1_UART_BAUDRATE 115200 #define STM32MP1_UART_BAUDRATE 115200
/*******************************************************************************
* STM32MP1 GIC-400
******************************************************************************/
#define STM32MP1_GICD_BASE U(0xA0021000)
#define STM32MP1_GICC_BASE U(0xA0022000)
#define STM32MP1_GICH_BASE U(0xA0024000)
#define STM32MP1_GICV_BASE U(0xA0026000)
/******************************************************************************* /*******************************************************************************
* STM32MP1 TZC (TZ400) * STM32MP1 TZC (TZ400)
******************************************************************************/ ******************************************************************************/
...@@ -149,10 +141,7 @@ enum ddr_type { ...@@ -149,10 +141,7 @@ enum ddr_type {
#define STM32MP1_TZC_ETH_ID U(10) #define STM32MP1_TZC_ETH_ID U(10)
#define STM32MP1_TZC_DAP_ID U(15) #define STM32MP1_TZC_DAP_ID U(15)
#define STM32MP1_MEMORY_NS 0 #define STM32MP1_FILTER_BIT_ALL U(3)
#define STM32MP1_MEMORY_SECURE 1
#define STM32MP1_FILTER_BIT_ALL 3
/******************************************************************************* /*******************************************************************************
* STM32MP1 SDMMC * STM32MP1 SDMMC
......
plat/st/stm32mp1/stm32mp1_gic.c
+ 51
− 5
View file @ 59a1cdf1
/* /*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <libfdt.h>
#include <platform_def.h> #include <platform_def.h>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h>
#include <drivers/arm/gicv2.h> #include <drivers/arm/gicv2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <lib/utils.h> #include <lib/utils.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <stm32mp1_dt.h>
#include <stm32mp1_private.h> #include <stm32mp1_private.h>
struct stm32_gic_instance {
uint32_t cells;
uint32_t phandle_node;
};
/****************************************************************************** /******************************************************************************
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts. * interrupts.
...@@ -22,19 +32,55 @@ static const interrupt_prop_t stm32mp1_interrupt_props[] = { ...@@ -22,19 +32,55 @@ static const interrupt_prop_t stm32mp1_interrupt_props[] = {
PLATFORM_G0_PROPS(GICV2_INTR_GROUP0) PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
}; };
static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; /* Fix target_mask_array as secondary core is not able to initialize it */
static unsigned int target_mask_array[PLATFORM_CORE_COUNT] = {1, 2};
static const gicv2_driver_data_t platform_gic_data = { static gicv2_driver_data_t platform_gic_data = {
.gicd_base = STM32MP1_GICD_BASE,
.gicc_base = STM32MP1_GICC_BASE,
.interrupt_props = stm32mp1_interrupt_props, .interrupt_props = stm32mp1_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(stm32mp1_interrupt_props), .interrupt_props_num = ARRAY_SIZE(stm32mp1_interrupt_props),
.target_masks = target_mask_array, .target_masks = target_mask_array,
.target_masks_num = ARRAY_SIZE(target_mask_array), .target_masks_num = ARRAY_SIZE(target_mask_array),
}; };
static struct stm32_gic_instance stm32_gic;
void stm32mp1_gic_init(void) void stm32mp1_gic_init(void)
{ {
int node;
void *fdt;
const fdt32_t *cuint;
struct dt_node_info dt_gic;
if (fdt_get_address(&fdt) == 0) {
panic();
}
node = dt_get_node(&dt_gic, -1, "arm,cortex-a7-gic");
if (node < 0) {
panic();
}
platform_gic_data.gicd_base = dt_gic.base;
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
panic();
}
platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2));
cuint = fdt_getprop(fdt, node, "#interrupt-cells", NULL);
if (cuint == NULL) {
panic();
}
stm32_gic.cells = fdt32_to_cpu(*cuint);
stm32_gic.phandle_node = fdt_get_phandle(fdt, node);
if (stm32_gic.phandle_node == 0U) {
panic();
}
gicv2_driver_init(&platform_gic_data); gicv2_driver_init(&platform_gic_data);
gicv2_distif_init(); gicv2_distif_init();
......
plat/st/stm32mp1/stm32mp1_pm.c
+ 5
− 7
View file @ 59a1cdf1
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -23,11 +23,9 @@ ...@@ -23,11 +23,9 @@
#include <boot_api.h> #include <boot_api.h>
#include <stm32mp1_private.h> #include <stm32mp1_private.h>
static uint32_t stm32_sec_entrypoint; static uintptr_t stm32_sec_entrypoint;
static uint32_t cntfrq_core0; static uint32_t cntfrq_core0;
#define SEND_SECURE_IT_TO_CORE_1 0x20000U
/******************************************************************************* /*******************************************************************************
* STM32MP1 handler called when a CPU is about to enter standby. * STM32MP1 handler called when a CPU is about to enter standby.
* call by core 1 to enter in wfi * call by core 1 to enter in wfi
...@@ -42,6 +40,7 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state) ...@@ -42,6 +40,7 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state)
* Enter standby state * Enter standby state
* dsb is good practice before using wfi to enter low power states * dsb is good practice before using wfi to enter low power states
*/ */
isb();
dsb(); dsb();
while (interrupt == GIC_SPURIOUS_INTERRUPT) { while (interrupt == GIC_SPURIOUS_INTERRUPT) {
wfi(); wfi();
...@@ -59,7 +58,7 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state) ...@@ -59,7 +58,7 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state)
/******************************************************************************* /*******************************************************************************
* STM32MP1 handler called when a power domain is about to be turned on. The * STM32MP1 handler called when a power domain is about to be turned on. The
* mpidr determines the CPU to be turned on. * mpidr determines the CPU to be turned on.
* call by core 0 to activate core 1 * call by core 0 to activate core 1
******************************************************************************/ ******************************************************************************/
static int stm32_pwr_domain_on(u_register_t mpidr) static int stm32_pwr_domain_on(u_register_t mpidr)
{ {
...@@ -102,8 +101,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr) ...@@ -102,8 +101,7 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
} }
/* Generate an IT to core 1 */ /* Generate an IT to core 1 */
mmio_write_32(STM32MP1_GICD_BASE + GICD_SGIR, gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP1_SECONDARY_CPU);
SEND_SECURE_IT_TO_CORE_1 | ARM_IRQ_SEC_SGI_0);
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
......
plat/st/stm32mp1/stm32mp1_security.c
+ 2
− 17
View file @ 59a1cdf1
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -65,22 +65,6 @@ static void init_tzc400(void) ...@@ -65,22 +65,6 @@ static void init_tzc400(void)
******************************************************************************/ ******************************************************************************/
static void early_init_tzc400(void) static void early_init_tzc400(void)
{ {
uint32_t rstsr, rst_standby;
rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
/* No warning if return from (C)STANDBY */
rst_standby = rstsr &
(RCC_MP_RSTSCLRR_STDBYRSTF | RCC_MP_RSTSCLRR_CSTDBYRSTF);
if (stm32mp1_clk_is_enabled(TZC1) && (rst_standby == 0U)) {
WARN("TZC400 port 1 clock already enable\n");
}
if (stm32mp1_clk_is_enabled(TZC2) && (rst_standby == 0U)) {
WARN("TZC400 port 2 clock already enable\n");
}
if (stm32mp1_clk_enable(TZC1) != 0) { if (stm32mp1_clk_enable(TZC1) != 0) {
ERROR("Cannot enable TZC1 clock\n"); ERROR("Cannot enable TZC1 clock\n");
panic(); panic();
...@@ -103,6 +87,7 @@ static void early_init_tzc400(void) ...@@ -103,6 +87,7 @@ static void early_init_tzc400(void)
STM32MP1_DDR_BASE + STM32MP1_DDR_BASE +
(STM32MP1_DDR_MAX_SIZE - 1U), (STM32MP1_DDR_MAX_SIZE - 1U),
TZC_REGION_S_RDWR, TZC_REGION_S_RDWR,
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID)); TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));
/* Raise an exception if a NS device tries to access secure memory */ /* Raise an exception if a NS device tries to access secure memory */
......
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