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Commit 6826b712 authored by Eberhard Stoll's avatar Eberhard Stoll
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stm32mp-t10xx: Adapt device tree files to new version

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fdts/stm32mp-som-t1000.dtsi
+ 53
− 39
View file @ 6826b712
......@@ -20,8 +20,8 @@
*/
/* force DDR settings */
#include "stm32mp157c-t1000-ddr-undef.h"
#include "stm32mp157c-t1000-ddr3-1x4Gb-1066-binG.h"
#include "stm32mp157c-t1000-ddr-undef.dtsi"
#include "stm32mp157c-t1000-ddr3-1x4Gb-1066-binG.dtsi"
#include "stm32mp15-ddr.dtsi"
#include <dt-bindings/power/stm32mp1-power.h>
......@@ -58,19 +58,21 @@
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
soc {
stgen: stgen@5C008000 {
compatible = "st,stm32-stgen";
reg = <0x5C008000 0x1000>;
status = "okay";
};
};
vdd_usb: regulator-vdd_usb {
compatible = "regulator-fixed";
regulator-name = "vdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
clocks {
clk_lse: clk-lse {
st,drive=<LSEDRV_MEDIUM_HIGH>;
};
clk_hse: clk-hse {
};
};
};
......@@ -121,7 +123,7 @@
CLK_SPI45_HSI
CLK_SPI6_HSI
CLK_I2C46_HSI
CLK_SDMMC3_PLL3R
CLK_SDMMC3_PLL4P
CLK_USBO_USBPHY
CLK_ADC_CKPER
CLK_CEC_LSE
......@@ -145,38 +147,45 @@
CLK_LPTIM45_PCLK3
>;
pll1:st,pll@0 {
cfg = < 2 80 0 1 1 1>; /* P=648MHz, Q=324Hz, R=324MHz */
compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = < 2 80 0 1 1 PQR(1,0,0)>; /* P=648MHz, Q=324Hz, R=324MHz */
/* frac = < 0x800 >; */
};
pll2:st,pll@1 {
cfg = < 2 65 1 1 0 7>; /* P=264MHz, Q=264Hz, R=528MHz */
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 1 0 PQR(1,1,1)>; /* P=264MHz, Q=264Hz, R=528MHz */
/* frac = < 0x1400 >; */
};
pll3:st,pll@2 {
cfg = < 1 49 2 2 1 3>; /* P=200MHz, Q=200MHz, R=300MHz */
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 49 2 2 1 PQR(1,1,0)>; /* P=200MHz, Q=200MHz, R=300MHz */
};
pll4:st,pll@3 {
cfg = < 5 124 9 9 9 3>; /* P=50MHz, Q=50Hz, R=50MHz */
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 5 124 9 9 9 PQR(1,1,0)>; /* P=50MHz, Q=50Hz, R=50MHz */
};
};
#endif /* RCC_FROM_MX */
&pwr {
pwr-supply = <&vdd>;
&pwr_regulators {
system_suspend_supported_soc_modes = <
STM32_PM_CSLEEP_RUN
STM32_PM_CSTOP_ALLOW_LP_STOP
STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR
>;
system_off_soc_mode = <STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF>;
vdd-supply = <&vdd>;
vdd_3v3_usbfs-supply = <&vdd_usb>;
};
#ifndef ETZPC_FROM_MX
/* Security specific */
/* Set all peripherals to sensible defaults (DECPROT_NS_RW)
* If you need special settings you have to define your own devicetree and tf-a
* variant
* If you need special settings you have to define your own devicetree and tf-a variant
*/
&etzpc{
st,decprot = <
......@@ -185,37 +194,40 @@
DECPROT(STM32MP1_ETZPC_ADC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TT_FDCAN_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TIM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DLYBQ_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_USART6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
/*"NS_R S_W" peripherals*/
DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
/*"Secured" peripherals*/
DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
/*"Mcu Isolation" peripherals*/
DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
/*Restriction: following IDs are not managed - please to use User-Section if needed:
STM32MP1_ETZPC_DMA1_ID, STM32MP1_ETZPC_DMA2_ID, STM32MP1_ETZPC_DMAMUX_ID,
/* Restriction: following IDs are not managed - please to use User-Section if needed:
STM32MP1_ETZPC_SRAMx_ID, STM32MP1_ETZPC_RETRAM_ID, STM32MP1_ETZPC_BKPSRAM_ID*/
/* USER CODE BEGIN etzpc_decprot */
/*STM32CubeMX generates a basic and standard configuration for ETZPC.
Additional device configurations can be added here if needed.
"etzpc" node could be also overloaded in "addons" User-Section.*/
/* USER CODE END etzpc_decprot */
>;
secure-status = "okay";
/* USER CODE BEGIN etzpc */
/* USER CODE END etzpc */
};
#endif /* ETZPC_FROM_MX */
......@@ -267,14 +279,14 @@
status = "okay";
secure-status = "okay";
/*opt word 59*/
/*opt word 59 - Kontron SOM ID */
som_id: som_id@ec{
reg=<0xec 0x4>;
status="okay";
secure-status="okay";
};
/*otp word 60*/
/*otp word 60 - Kontron Board ID */
board_id: board_id@f0{
reg=<0xf0 0x4>;
status="okay";
......@@ -282,18 +294,20 @@
};
};
&tamp{
status = "okay";
secure-status = "okay";
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_som>;
resets = <&rcc UART4_R>;
status = "okay";
};
/* qspi flash */
&qspi {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&quadspi_pins_som>;
status = "okay";
......@@ -336,9 +350,9 @@
};
&iwdg2 {
instance = <0x2>;
timeout-sec = <0x20>;
status = "okay";
secure-status = "okay";
};
&rcc {
......
fdts/stm32mp-t1000-fw-config.dts 0 → 100644
+ 11
− 0
View file @ 6826b712
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
#include "stm32mp15-ddr-512m-fw-config.dts"
fdts/stm32mp-t1000.dts
+ 1
− 1
View file @ 6826b712
......@@ -7,7 +7,7 @@
* revision : 03
*
* Kontron Electronics GmbH
* Copyright 2019 Kontron Electronics GmbH. All rights reserved.
* Copyright 2021 Kontron Electronics GmbH. All rights reserved.
*/
/* Include CubeMX board configuration
......
fdts/stm32mp15-mx.h → fdts/stm32mp15-mx.dtsi
+ 0
− 0
View file @ 6826b712
File moved
fdts/stm32mp157c-t1000-ddr3-1x4Gb-1066-binG.h → fdts/stm32mp157c-t1000-ddr3-1x4Gb-1066-binG.dtsi
+ 1
− 1
View file @ 6826b712
......@@ -19,7 +19,7 @@
* Save Date: 2019.04.04, save Time: 16:24:24
*/
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 528Mhz K4B4G1646E (v1,1066-7-7-7,cal)"
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 528000kHz K4B4G1646E (v1,1066-7-7-7,cal)"
#define DDR_MEM_SPEED 528000
#define DDR_MEM_SIZE 0x20000000
......
fdts/stm32mp157c-t1000-som-minimal-mx-fw-config.dts 0 → 100644
+ 11
− 0
View file @ 6826b712
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
#include "stm32mp15-ddr-512m-fw-config.dts"
fdts/stm32mp157c-t1000-som-minimal-mx.dts
+ 48
− 16
View file @ 6826b712
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-mx.h"
#include <dt-bindings/soc/st,stm32-etzpc.h>
#include "stm32mp15-mx.dtsi"
#include "stm32mp157c.dtsi"
#include "stm32mp157cad-pinctrl.dtsi"
#include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xxad-pinctrl.dtsi"
#include "stm32mp15-ddr.dtsi"
#include "stm32mp157c-security.dtsi"
/* USER CODE BEGIN includes */
/* USER CODE END includes */
/ {
model = "STMicroelectronics custom STM32CubeMX board";
model = "STMicroelectronics custom STM32CubeMX board - openstlinux-5.10-dunfell-mp1-21-03-31";
compatible = "st,stm32mp157c-t1000-som-minimal-mx", "st,stm32mp157";
/* USER CODE BEGIN root */
......@@ -28,14 +34,16 @@
/* USER CODE END clocks */
clk_lse: clk-lse {
/* USER CODE BEGIN clocks */
/* USER CODE END clocks */
st,drive=<LSEDRV_MEDIUM_HIGH>;
st,drive = < LSEDRV_MEDIUM_HIGH >;
/* USER CODE BEGIN clk_lse */
/* USER CODE END clk_lse */
};
clk_hse: clk-hse {
/* USER CODE BEGIN clocks */
/* USER CODE END clocks */
/* USER CODE BEGIN clk_hse */
/* USER CODE END clk_hse */
};
};
......@@ -186,16 +194,24 @@
CLK_LPTIM45_DISABLED
>;
pll1:st,pll@0 {
cfg = < 2 80 0 1 1 1>;
compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = < 2 80 0 1 1 PQR(1,0,0) >;
};
pll2:st,pll@1 {
cfg = < 2 65 1 1 0 7>;
compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 1 0 PQR(1,1,1) >;
};
pll3:st,pll@2 {
cfg = < 1 49 2 2 1 1>;
compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 49 2 2 1 PQR(1,0,0) >;
};
pll4:st,pll@3 {
cfg = < 5 124 9 9 9 1>;
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 5 124 9 9 9 PQR(1,0,0) >;
};
};
......@@ -212,6 +228,8 @@
/*"Non Secured" peripherals*/
DECPROT(STM32MP1_ETZPC_ADC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_I2C2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
......@@ -221,9 +239,15 @@
DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
/*"NS_R S_W" peripherals*/
DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
/*"Secured" peripherals*/
DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
/*"Mcu Isolation" peripherals*/
DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
/*Restriction: following IDs are not managed - please to use User-Section if needed:
STM32MP1_ETZPC_DMA1_ID, STM32MP1_ETZPC_DMA2_ID, STM32MP1_ETZPC_DMAMUX_ID,
STM32MP1_ETZPC_SRAMx_ID, STM32MP1_ETZPC_RETRAM_ID, STM32MP1_ETZPC_BKPSRAM_ID*/
/* USER CODE BEGIN etzpc_decprot */
......@@ -291,6 +315,14 @@
/* USER CODE END sdmmc1 */
};
&tamp{
status = "okay";
secure-status = "okay";
/* USER CODE BEGIN tamp */
/* USER CODE END tamp */
};
&uart4{
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_mx>;
......
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