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Commit 7665ab6b authored by Lionel Debieve's avatar Lionel Debieve Committed by Sebastien Pasdeloup
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stm32mp: Add secure secret provisioning feature


This patch adds changes to support the secure secret
provisioning (SSP).

Add a specific platform build that constructs a dedicated BL2
image to support the SSP feature.
Supported boot mode is limited to serial boot (USB or UART).

Signed-off-by: default avatarLionel Debieve <lionel.debieve@st.com>
Change-Id: I85de08efd8d4183cd7e1bc0b6f17d247669b82ce
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/185336


Reviewed-by: default avatarCITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: default avatarCIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: default avatarYann GAUTIER <yann.gautier@st.com>
parent 481580b9
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2020 - All Rights Reserved
*/
/ {
cpus {
/delete-node/ cpu@1;
};
#if STM32MP_USB_PROGRAMMER
aliases {
/delete-property/ serial1;
};
#endif
/delete-node/ cpu0_opp_table;
nvmem_layout@0 {
/delete-property/ nvmem-cells;
/delete-property/ nvmem-cell-names;
nvmem-cells = <&cfg0_otp>,
<&part_number_otp>,
<&monotonic_otp>,
<&nand_otp>,
<&uid_otp>,
<&package_otp>,
<&hw2_otp>,
<&pkh_otp>,
<&cfg2_otp>,
<&ssp_otp>,
<&chip_otp>,
<&rma_otp>;
nvmem-cell-names = "cfg0_otp",
"part_number_otp",
"monotonic_otp",
"nand_otp",
"uid_otp",
"package_otp",
"hw2_otp",
"pkh_otp",
"cfg2_otp",
"ssp_otp",
"chip_otp",
"rma_otp";
};
/delete-node/ psci;
soc {
efuse@5c005000 {
cfg2_otp: cfg2_otp@8 {
reg = <0x8 0x4>;
};
ssp_otp: ssp_otp@20 {
reg = <0x20 0x4>;
};
chip_otp: chip_otp@a0 {
reg = <0xa0 0x40>;
};
rma_otp: rma_otp@e0 {
reg = <0xe0 0x4>;
};
};
/delete-node/ timer@40006000;
/delete-node/ timer@44006000;
/delete-node/ pwr_mcu@50001014;
/delete-node/ cryp@54001000;
/delete-node/ rng@54003000;
/delete-node/ memory-controller@58002000;
/delete-node/ spi@58003000;
/delete-node/ sdmmc@58005000;
/delete-node/ sdmmc@58007000;
/delete-node/ ddr@5a003000;
/delete-node/ spi@5c001000;
/delete-node/ rtc@5c004000;
/delete-node/ etzpc@5c007000;
/delete-node/ stgen@5c008000;
/delete-node/ i2c@5c009000;
/delete-node/ tamp@5c00a000;
#if STM32MP_USB_PROGRAMMER
/delete-node/ serial@4000e000;
/delete-node/ serial@4000f000;
/delete-node/ serial@40011000;
/delete-node/ serial@40018000;
/delete-node/ serial@40019000;
/delete-node/ serial@44003000;
/delete-node/ serial@5c000000;
#endif
#if STM32MP_UART_PROGRAMMER
/delete-node/ usb-otg@49000000;
/delete-node/ usbphyc@5a006000;
#endif
pin-controller@50002000 {
/delete-node/ fmc-0;
/delete-node/ qspi-clk-0;
/delete-node/ qspi-bk1-0;
/delete-node/ qspi-bk2-0;
/delete-node/ rtc-out2-rmp-pins-0;
/delete-node/ sdmmc1-b4-0;
/delete-node/ sdmmc1-dir-0;
/delete-node/ sdmmc2-b4-0;
/delete-node/ sdmmc2-b4-1;
/delete-node/ sdmmc2-d47-0;
#if STM32MP_USB_PROGRAMMER
/delete-node/ uart7-0;
/delete-node/ uart7-1;
/delete-node/ usart2-0;
/delete-node/ usart3-0;
/delete-node/ usart3-1;
#endif
#if STM32MP_UART_PROGRAMMER
/delete-node/ usbotg_hs-0;
/delete-node/ usbotg-fs-dp-dm-0;
#endif
};
};
};
......@@ -335,15 +335,278 @@ BOOT_API_MCIC_RETRAM_REGION_TO_HASH_IN_BYTES_TAMP_BCK_REG_IDX 23
/* 'K' 'B' 'U' 'P' -.> 'PUBK' */
#define BOOT_API_CTX_SSP_CMD_CALC_CHIP_PUBK 0x4B425550
#if STM32MP_SSP
/* 'V' 'O' 'R' 'P' -.> 'PROV' */
#define BOOT_API_CTX_SSP_CMD_PROV_SECRET 0x564F5250
/*
* Possible values of boot context field
* 'ssp_config_ptr_in->ssp_cmd' written by bootROM as Acknowledge
* of a request of SSP by FSBL.
*/
/* Written by bootROM on SSP error */
#define BOOT_API_CTX_SSP_CMD_INVALID 0x00000000
/*
* 'A' 'B' 'U' 'P' -.> 'PUBA' : ACK of ECIES_CHIP_PUBK calculation
* request by bootROM.
*/
#define BOOT_API_CTX_SSP_CMD_CALC_CHIP_PUBK_ACK 0x41425550
/*
* 'A' 'O' 'R' 'P' -.> 'PROA' : ACK of OEM Secret Provisioning request
* by bootROM.
*/
#define BOOT_API_CTX_SSP_CMD_PROV_SECRET_ACK 0x414F5250
/*
* Constants required for SSP
*/
/* '.' 'P' 'S' 'S' -.> 'SSP.' */
#define BOOT_API_SSP_BLOB_LICENSE_TYPE_SSP_NORMAL 0x2E505353
/* 'L' 'P' 'S' 'S' -.> 'SSPL' */
#define BOOT_API_SSP_BLOB_LICENSE_TYPE_SSP_LIVE 0x4C505353
/* version 1 */
#define BOOT_API_SSP_LICENSE_LAYOUT_VERSION_TO_MATCH 0x00000001
/* 'P' 'P' 'S' 'S' -.> 'SSPP' */
#define BOOT_API_SSP_BLOB_PAYLOAD_MAGIC_SSP 0x50505353
/* IV AES on 128 bits = 16 bytes and KEY AES on 128 bits = 16 bytes */
#define BOOT_API_SSP_ENCRYPTED_IV_AND_KEY_SIZE_BYTES 32
/* version 1 */
#define BOOT_API_SSP_PAYLOAD_PROTOCOL_VERSION_TO_MATCH 0x00000001
/*
* Scalar in Elliptic curve cryptography is an integer (often a Prime)
* the number of bytes of this scalar is defined below.
*/
#define BOOT_API_SSP_SCALAR_SIZE_BYTES 32
/*
* In Elliptic curve cryptography coordinates of points are 2D P
* (Px, Py) as concatenation of two scalars.
*/
#define BOOT_API_SSP_EC_COORDINATE_SIZE_BYTES \
(2 * BOOT_API_SSP_SCALAR_SIZE_BYTES)
/* In Elliptic curve cryptography Private Keys are scalars */
#define BOOT_API_SSP_PRIVK_KEY_SIZE_BYTES \
BOOT_API_SSP_SCALAR_SIZE_BYTES
/*
* In ECIES algorithm the Shared Secret (SS) is
* the x coordinate (Px) of a point P(Px,Py) obtained on reference
* chosen NIST-P256 Elliptic curve.
*/
#define BOOT_API_SSP_ECDH_SHARED_SECRET_SIZE_BYTES \
BOOT_API_SSP_SCALAR_SIZE_BYTES
/*
* In Elliptic curve cryptography Public Keys are Points on chosen
* Elliptic curve P(x,y).
* Public Key is the x, y coordinates concatenated
* Ecies_eph_pubk and OEM_ECDSA_PUBK are each 64 bytes = 512 bits key
* sizes.
*/
#define BOOT_API_SSP_PUBK_KEY_SIZE_BYTES \
BOOT_API_SSP_EC_COORDINATE_SIZE_BYTES
/*
* Size in bytes of ECIES_Chip_pubk obtained from bootROM at end of SSP
* phase 1 : Chip public key calculation.
*/
#define BOOT_API_SSP_ECIES_CHIP_PUBK_SIZE_BYTES \
BOOT_API_SSP_PUBK_KEY_SIZE_BYTES
/* AES-GCM authentication tag size is 16 bytes = 128 bits */
#define BOOT_API_SSP_AES_GCM_AUTH_TAG_SIZE_BYTES 16
/* AES-GCM Symmetric Key size is 16 bytes = 128 bits */
#define BOOT_API_SSP_AES_GCM_KEY_SIZE_BYTES 16
/* AES-GCM Initialization Vector (IV) size is of 16 bytes = 128 bits */
#define BOOT_API_SSP_AES_GCM_IV_SIZE_BYTES 16
/*
* 88 bytes (license_type, live_session_id, license_version,
* fsbl_min_version, rfu[8], eph_ecies_pubk[])
*/
#define BOOT_API_SSP_AES_GCM_LICENSE_AAD_NB_BYTES_FROM_LICENSE 88
/*
* 32 bytes AAD License Secret from 2nd round KDF-SHA-256
* from ECDH Shared Secret hence KDF[32..63] aka "Authorization Token"
*/
#define BOOT_API_SSP_AES_GCM_LICENSE_AAD_NB_BYTES_FROM_KDF 32
/*
* Total License AAD size = 88 + 32 = 120 bytes
*/
#define BOOT_API_SSP_AES_GCM_LICENSE_AAD_SIZE_BYTES \
(BOOT_API_SSP_AES_GCM_LICENSE_AAD_NB_BYTES_FROM_LICENSE + \
BOOT_API_SSP_AES_GCM_LICENSE_AAD_NB_BYTES_FROM_KDF)
/*
* AAD for Payload size : composed of :
* payload_magic, payload_protocol_version, oem_ecdsa_pubk[], oem_secret_size
* = 4 + 4 + 64 + 4 = 76 bytes AAD for Payload
*/
#define BOOT_API_SSP_AES_GCM_PAYLOAD_AAD_SIZE_BYTES 76
/*
* OEM Secrets max size in bytes :
* [OTP[95:59] + OTP_CFG56 (RMA Unlock and Relock passwords)] x 4 bytes
* by OTP word = 152 bytes
*/
#define BOOT_API_SSP_OEM_SECRETS_MAX_SIZE_BYTES 152
/*
* Possible values of boot context field 'ssp_status'
* as can be read by FSBL-SSP
*/
#define BOOT_API_CTX_SSP_STATUS_NO_SSP 0
#define BOOT_API_CTX_SSP_STATUS_CHIP_PUBK_CALC_FINISHED 1
#define BOOT_API_CTX_SSP_STATUS_OEM_SEC_PROV_FINISHED 2
#define BOOT_API_CTX_SSP_STATUS_OEM_SEC_PROV_FORBIDDEN 3
/*
* Reserved size for future use
*/
#define BOOT_API_SSP_HSM_OEM_RFU_SIZE 8
/*
* Exported types
*/
/*
* SSP related definitions
*/
/*
* SSP BLOB License structure : Binary Large OBject License structure
* Should be written by FSBL-SSP to provide bootROM with SSP OEM Secret
* provisioning.
* License information data, the structure is read by bootROM.
*/
typedef struct {
/*
* License Type provided by HSM-OEM tool
* should match Normal SSP License of Live SSP License.
*/
uint32_t license_type;
/* Live Session ID provided by HSM-OEM tool */
uint32_t live_session_id;
/*
* Version of the License Protocol (Structure)
* should be incremented each time a new.
*/
uint32_t license_version;
/*
* Minimum FSBL version to be compared
* with FSBL Header field 'imageVersion'.
*/
uint32_t fsbl_min_version;
/* RFU provided by HSM-OEM tool */
uint8_t rfu[BOOT_API_SSP_HSM_OEM_RFU_SIZE];
/*
* Ephemeral ECIES Public Key from HSM-OEM
* 64 bytes = 512 bits.
*/
uint8_t eph_ecies_pubk[BOOT_API_SSP_PUBK_KEY_SIZE_BYTES];
/*
* Encrypted (IV,Key) : with Shared Secret based on
* 'Ephemeral ECIES Key pair' and 'ECIES Chip Key pair'.
*/
uint8_t encrypted_iv_and_key
[BOOT_API_SSP_ENCRYPTED_IV_AND_KEY_SIZE_BYTES];
/*
* AUTH_TAG AES-GCM from encryption of (IV, Key)
* in HSM-OEM with License AAD scheme
* License Tag is 16 bytes = 128 bits.
*/
uint8_t license_tag[BOOT_API_SSP_AES_GCM_AUTH_TAG_SIZE_BYTES];
} boot_api_ssp_blob_license_t;
/*
* SSP BLOB Payload structure : Binary Large OBject Payload Structure
* Should be written by FSBL-SSP to provide bootROM with SSP OEM Secret
* provisioning input data, the structure is read by bootROM
* The BLOB Payload size is fixed to a max size of 244 bytes based
* on a max number of bytes of OEM secret derived from OTP upper free
* area in STM32MP15xx cut 2.0.In this table oem_encrypted_secrets[]
* of max size only the first 'p_blob_payload->oem_secret_size_bytes'
* bytes will be considered and used by bootROM.
*/
typedef struct {
/*
* BLOB Payload Magic : for memory validity check of BLOB Payload
* to match against BOOT_API_SSP_BLOB_PAYLOAD_MAGIC_SSP by bootROM.
*/
uint32_t payload_magic;
/*
* SSP Payload protocol version : on 32 bits
* to be checked by bootROM for equality with
* BOOT_API_SSP_PAYLOAD_PROTOCOL_VERSION_TO_MATCH
* ie : 0x00000001 : version 1 of SSP Payload
*/
uint32_t payload_protocol_version;
/*
* OEM_ECDSA_PUBK Public Key defined by OEM
* 64 bytes = 512 bits
*/
uint8_t oem_ecdsa_pubk[BOOT_API_SSP_PUBK_KEY_SIZE_BYTES];
/*
* Size of Table of OEM Secrets encrypted with AES-GCM (Key,IV) from
* License field 'encrypted_iv_and_key[]'
* should be <= BOOT_API_SSP_OEM_SECRETS_MAX_SIZE_BYTES:
* is verified by bootROM.
*/
uint32_t oem_secret_size_bytes;
/*
* AUTH_TAG AES-GCM computed by HSM-OEM when encrypting OEM Secrets with
* (Key,IV) using special AAD scheme for Payload.
* 16 bytes = 128 bits
*/
uint8_t payload_tag[BOOT_API_SSP_AES_GCM_AUTH_TAG_SIZE_BYTES];
/*
* OEM Secrets encrypted with AES-GCM (IV, Key) from
* License field 'encrypted_iv_and_key[]'.
* The payload size is 'oem_secret_size_bytes'
* should be <= BOOT_API_SSP_OEM_SECRETS_MAX_SIZE_BYTES =
* 152 bytes : OEM Secrets max size in bytes :
* [OTP_CFG56, OTP_CFG59, OTP_CFG60..95] x 4 bytes by OTP word.
*/
uint8_t oem_encrypted_secrets[BOOT_API_SSP_OEM_SECRETS_MAX_SIZE_BYTES];
} boot_api_ssp_blob_payload_t;
#endif
/* SSP Configuration structure */
typedef struct {
/* SSP Command*/
uint32_t ssp_cmd;
#if STM32MP_SSP
/* ECIES chip public key */
uint8_t *p_chip_pubk;
/* Blob License Address */
boot_api_ssp_blob_license_t *p_blob_license;
/* Blob Payload Address */
boot_api_ssp_blob_payload_t *p_blob_payload;
/* Secrets Decrypted Address */
uint8_t *p_ssp_oem_secrets_decrypted;
/* Reserved for Future Use (RFU) */
uint32_t padding_rfu;
#else
uint8_t reserved[20];
#endif
} boot_api_ssp_config_t;
/*
......
......@@ -38,6 +38,9 @@ STM32MP_DDR_DUAL_AXI_PORT:= 1
STM32_HEADER_VERSION_MAJOR:= 1
STM32_HEADER_VERSION_MINOR:= 0
# STM32 Secure Secret Provisioning mode (SSP)
STM32MP_SSP ?= 0
ifeq ($(AARCH32_SP),sp_min)
# Disable Neon support: sp_min runtime may conflict with non-secure world
TF_CFLAGS += -mfloat-abi=soft
......@@ -157,6 +160,7 @@ $(eval $(call assert_booleans,\
STM32MP_USB_PROGRAMMER \
STM32MP_USE_STM32IMAGE \
STM32MP_DDR_DUAL_AXI_PORT \
STM32MP_SSP \
)))
$(eval $(call assert_numerics,\
......@@ -181,6 +185,7 @@ $(eval $(call add_defines,\
STM32_TF_VERSION \
STM32MP_USE_STM32IMAGE \
STM32MP_DDR_DUAL_AXI_PORT \
STM32MP_SSP \
)))
# Include paths and source files
......@@ -347,6 +352,10 @@ BL2_SOURCES += lib/optee/optee_utils.c
BL2_SOURCES += plat/st/stm32mp1/stm32mp1_critic_power.c
BL2_SOURCES += plat/st/stm32mp1/stm32mp1_critic_power_wrapper.S
ifeq ($(STM32MP_SSP),1)
include plat/st/stm32mp1/stm32mp1_ssp.mk
endif
# Compilation rules
.PHONY: check_dtc_version stm32image clean_stm32image check_boot_device
.SUFFIXES:
......
......@@ -27,10 +27,6 @@
#include "bsec_svc.h"
#define SSP_OTP_REQ BIT(BOOT_API_OTP_SSP_REQ_BIT_POS)
#define SSP_OTP_SUCCESS BIT(BOOT_API_OTP_SSP_SUCCESS_BIT_POS)
#define SSP_OTP_MASK (SSP_OTP_REQ | SSP_OTP_SUCCESS)
enum bsec_ssp_status {
BSEC_NO_SSP = 0,
BSEC_SSP_SET,
......
......@@ -130,6 +130,7 @@ enum ddr_type {
(STM32MP_PARAM_LOAD_SIZE + \
STM32MP_HEADER_SIZE))
#if !STM32MP_SSP
#if STM32MP_USE_STM32IMAGE
#define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */
......@@ -173,6 +174,7 @@ enum ddr_type {
#define STM32MP_BL32_SIZE U(0x0001A000) /* 100 KB for BL32 */
#endif
#endif /* STM32MP_USE_STM32IMAGE */
#endif /* STM32MP_SSP */
#if defined(IMAGE_BL2)
#define STM32MP_DEFAULT_XLAT U(2) /* 8 KB for mapping */
......@@ -212,6 +214,29 @@ enum ddr_type {
#endif
#endif
#if STM32MP_SSP
#define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */
#define STM32MP_BL2_DTB_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_HEADER_RESERVED_SIZE)
#define STM32MP_BL2_RO_SIZE U(0x0000C000) /* 48 Ko for BL2 */
#define STM32MP_BL2_RO_BASE STM32MP_BL2_DTB_BASE + \
STM32MP_BL2_DTB_SIZE
#define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
STM32MP_BL2_RO_SIZE)
#define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
STM32MP_BL2_RW_BASE)
#define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
#define TF_A_MAPPING_START STM32MP_BL2_DTB_BASE
#else
#if STM32MP_USE_STM32IMAGE
/* DTB initialization value */
#define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
......@@ -240,6 +265,7 @@ enum ddr_type {
#endif
#define TF_A_MAPPING_START STM32MP_BL2_DTB_BASE
#endif /* STM32MP_USE_STM32IMAGE */
#endif /* STM32MP_SSP */
#define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \
STM32MP_SYSRAM_SIZE - \
......@@ -429,11 +455,35 @@ enum ddr_type {
#define UID_OTP "uid_otp"
#define PKH_OTP "pkh_otp"
#define BOARD_ID_OTP "board_id"
#define CFG2_OTP "cfg2_otp"
#define SSP_OTP "ssp_otp"
#define CHIP_CERTIFICATE_OTP "chip_otp"
#define RMA_OTP "rma_otp"
/* OTP mask */
/* CFG0 */
#define CFG0_CLOSED_DEVICE BIT(6)
/* CFG2 */
#define OTP_CFG2_SEC_COUNTER_MASK GENMASK_32(27, 20)
#define OTP_CFG2_SEC_COUNTER_SHIFT U(20)
#define OTP_CFG2_ST_KEY_MASK GENMASK_32(31, 28)
#define OTP_CFG2_ST_KEY_SHIFT U(28)
/* SSP */
#define SSP_OTP_REQ BIT(BOOT_API_OTP_SSP_REQ_BIT_POS)
#define SSP_OTP_SUCCESS BIT(BOOT_API_OTP_SSP_SUCCESS_BIT_POS)
#define SSP_OTP_MASK GENMASK_32(BOOT_API_OTP_SSP_SUCCESS_BIT_POS, \
BOOT_API_OTP_SSP_REQ_BIT_POS)
#define SSP_OTP_SECRET_BASE U(59)
#define SSP_OTP_SECRET_END U(95)
/* CHIP_CERT */
#define CHIP_CERTIFICATE_MAX_SIZE U(0x40)
/* RMA */
#define RMA_OTP_MASK GENMASK_32(29, 0)
/* PART NUMBER */
#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
#define PART_NUMBER_OTP_PART_SHIFT 0
......
This diff is collapsed.
#
# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ST_VERSION := r1.0-ssp
VERSION_STRING := v${VERSION_MAJOR}.${VERSION_MINOR}-${ST_VERSION}(${BUILD_TYPE}):${BUILD_STRING}
# Required to use BL2_IN_XIP_MEM
BL2_IN_XIP_MEM := 1
SEPARATE_CODE_AND_RODATA := 1
TRUSTED_BOARD_BOOT := 0
# Macros and rules to build TF-A binary
STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-ssp-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
PLAT_BL_COMMON_SOURCES := common/fdt_wrappers.c \
plat/st/common/stm32mp_common.c \
plat/st/stm32mp1/stm32mp1_private.c
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
PLAT_BL_COMMON_SOURCES += lib/cpus/aarch32/cortex_a7.S
PLAT_BL_COMMON_SOURCES += drivers/st/uart/aarch32/stm32_console.S
PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \
drivers/clk/clk.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/st/bsec/bsec2.c \
drivers/st/clk/stm32mp_clkfunc.c \
drivers/st/gpio/stm32_gpio.c \
drivers/st/i2c/stm32_i2c.c \
drivers/st/iwdg/stm32_iwdg.c \
drivers/st/pmic/stm32mp_pmic.c \
drivers/st/pmic/stpmic1.c \
drivers/st/regulator/stm32mp_dummy_regulator.c \
drivers/st/regulator/stm32mp_regulator.c \
drivers/st/reset/stm32mp1_reset.c \
plat/st/common/stm32mp_dt.c \
plat/st/common/stm32mp_shres_helpers.c \
plat/st/stm32mp1/stm32mp1_dbgmcu.c \
plat/st/stm32mp1/stm32mp1_helper.S \
plat/st/stm32mp1/stm32mp1_syscfg.c
PLAT_BL_COMMON_SOURCES += drivers/st/clk/stm32mp1_clk.c
BL2_SOURCES := drivers/io/io_storage.c \
drivers/st/crypto/stm32_hash.c \
plat/st/stm32mp1/stm32mp1_ssp.c
ifeq (${STM32MP_UART_PROGRAMMER},1)
BL2_SOURCES += drivers/st/uart/stm32_uart.c \
plat/st/common/stm32cubeprogrammer_uart.c
endif
ifeq (${STM32MP_USB_PROGRAMMER},1)
BL2_SOURCES += drivers/st/usb_dwc2/usb_dwc2.c \
lib/usb/usb_core.c \
lib/usb/usb_st_dfu.c \
plat/st/common/stm32cubeprogrammer_usb.c \
plat/st/stm32mp1/stm32mp1_usb.c
endif
BL2_DTSI := stm32mp15-ssp-bl2.dtsi
check_boot_ssp:
@if ([ ${STM32MP_UART_PROGRAMMER} = 1 ] && [ ${STM32MP_USB_PROGRAMMER} = 1 ]) || \
([ ${STM32MP_UART_PROGRAMMER} = 0 ] && [ ${STM32MP_USB_PROGRAMMER} = 0 ]); then \
echo "Error selecting serial boot device"; \
false; \
fi
bl2: check_boot_ssp
${BUILD_PLAT}/stm32mp1-ssp-%.o: ${BUILD_PLAT}/fdts/%-bl2.dtb plat/st/stm32mp1/stm32mp1.S bl2
@echo " SSP AS stm32mp1.S"
${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \
-DDTB_BIN_PATH=\"$<\" \
-c plat/st/stm32mp1/stm32mp1.S -o $@
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