Public key brainpool ecdsa DER certificate are 92 byte long:
OID for brainpool curve are 1 byte bigger than the one for NIST curve.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Change-Id: Ifad51da3c576d555da9fc519d2df3d9a0e6ed91b
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184837


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Tested-by: Lionel DEBIEVE <lionel.debieve@st.com>

with platform format PK

In some platform the digest of the public key saved in the OTP is not
the the digest of the exact same public key buffer needed to check the
signature.  Typically, check signature may need a BER encapsulated
public key, but the hash saved in OTP may be the hash of the plain
public key.  Add a new platform weak function to transform the public
key buffer used by verify_signature to a buffer which hash is saved in
OTP.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Change-Id: I71017b41e3eca9398cededf317ad97e9b511be5f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184836


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Move the fw_config authentication structure into the common part.
Without BL1, the fw_config will be added into the BL2 firmware.
It will be loaded from FIP and authenticated in BL2.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I3b8f8e99961d28d3d15a6dbff06b0d9cdda20881
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184832


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Nicolas TOROMANOFF <nicolas.toromanoff@st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Tested-by: Nicolas TOROMANOFF <nicolas.toromanoff@st.com>

Add the system reset management into the stm32mp
reset driver.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I748f10de2398e1323160f479f99e92abd2f65dca
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184412


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Gabriel FERNANDEZ <gabriel.fernandez@st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Change call of:
stm32mp_clk_enable() / stm32mp_clk_disable() / stm32mp_clk_get_rate()
by
clk_enable() / clk_disable() / clk_get_rate()

Change-Id: I15d2ce57b9499211fa522a1b53eeee9cf584c111
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/182346


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Tested-by: Yann GAUTIER <yann.gautier@st.com>

Introduce a minimal clock framework.

Change-Id: I5119a2aeaf103ceaae7a60d9e423caf0c148d794
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/182345


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Tested-by: Yann GAUTIER <yann.gautier@st.com>

Add bindings that will be used to define DDR regions
and their access rights.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I745a7e580ef2b9e251d53db12c5a0a86dfe34463
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/178512


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Remove access and check linked to backup register. RAM must
focus on DDR self refresh status based on the wake-up
state. Add a new export function to inform about the self
refresh state.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Id2ef8c42ddcd5e24a9250ba07a048bd9b27d9dec
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/180503


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Add a new function that allows to enable or disabled filters on
configured regions dynamically. This will avoid to reconfigure
the entire attribute and just manage to enable/disable filters.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: If0937ca755bec6c45d3649718147108459682fff
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/178510


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.

Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Change-Id: I6486de200ddde5526fe64f4be8cb85fa3fe89431
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Add regsiters defines and helpers to check if a virtual address is secured.

Change-Id: I14d36dee5cb3356ce41054de9157b58b47ac463f
Signed-off-by: Yann Gautier <yann.gautier@st.com>

This function is under LOG_LEVEL_VERBOSE flag, to help debugging clocks.

Change-Id: I4a898c883bbecff8ebfaff156c97947e51697f03
Signed-off-by: Yann Gautier <yann.gautier@st.com>

psci_is_last_on_cpu() function becomes public.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I393219d0ea01207c08289e91d96f0a33888de10f
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/176501


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

dt_pmic_find_supply() finds in the FDT the supply name related to a
regulator name.
pmic_set_regulator_min_voltage() sets target supply to its min voltage
specified in the FDT by property "regulator-min-microvolt".

Change-Id: Ic5fcabb7b2353deb1af20b7cc76e5bceca70bc77
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/160673


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Alignment with Kernel DT bindings.

Change-Id: Iae246dbc9c55c4ed7e52ccbee1d77e7e478c1dd9
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/160719


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Tested-by: Yann GAUTIER <yann.gautier@st.com>

Define DDR Self Refresh (SR) mode read/set/save/restore API functions.
At the end of DDR initialization in BL2, switch SR mode to the one
indicated by DDR updated registers. Save mode at BL32 init.
When entering in cstop/cstandby, switch to SSR (Software).
When exiting, go back to the saved mode.

Change-Id: Iadd795d20fdea2d7be30c1ba6f02eb172e33f4b1
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Change-Id: Iad0dc8dda5f2f7e30a2397e1b096ec7ca6a042b2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

This was previously done in ddr_standby_sr_entry().
It is now done as a separate function.
This will ease the DDR Self-Refresh entry for platforms having monitor in
DDR.

Change-Id: I69ccf0f33d20584579626b973a4295ede351a803
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>

Instead of transmitting an 'enum stm32mp_osc_id', just send
directly the clock name with a 'const char *'

Change-Id: I866b05cbb1685a9b9f80e63dcd5ba7b1d35fc932
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/170250


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com>

Don't switch to MPUDIV/PLL1P in suspend/resume mode.
Non-secure is in charge of requesting MPU lowest OPP when suspending.

Change-Id: Iad47122c25d6f03247b7754a77e8d415c3720850
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

Adding the MCU hold boot management through a SCMI dedicated
reset domain. Remove the associated RCC SMC service.

Minor: Fix the panic when trying to checking access to avoid
non-secure world panic trigger.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I70fe10602eaa0e76ef2aad9cd8c1b0454dae190a

This change makes SYSCFG clock being disabled when IO compensation
is disabled when entering system low power state.

SYSCFG clock is non-secure as its related SoC interface register
can be read/write by non-secure world. A consequence is that
the clock is never disabled by stm32mp1 clock driver.

Replace functions stm32mp1_clk_enable_non_secure() and
stm32mp1_clk_disable_non_secure(), used only for this SYSCFG
clock control, with stm32mp1_clk_force_enable() and
stm32mp1_clk_force_disable(). These functions gate the target
clock without considering the software reference counting.

Change-Id: I0d0a6ea3c598996fe475fc23613163df07631728
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

In case of stop mode, PLL3, PLL4 are stopped and reset to default
value. They must be saved and restarted, MSS clock selection must
be also restored.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I30ba31403a9e3277663319c06bca01c5ab81d070

When RCC[TZEN] is enabled secure world needs to save the secure and
non-secure clock configuration settings and restore them when
resuming.

Function stm32mp1_clk_mpu_suspend()/stm32mp1_clk_mpu_resume() are
made local and renamed clk_mpu_suspend()/clk_mpu_resume(). The
overall clock configuration is saved with stm32mp1_clock_suspend()
and restored with stm32mp1_clock_resume().

Change-Id: I1fc0c693c59ffe972961c2b23f30a39a520f3aaa
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to
USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are
needed since manipulated during the suspend/resume power sequence
as per FDT description for stm32mp15x-xxx boards from
STMicroelectronics.

Change-Id: I6217de707e49882bd5a9100db43e0d354908800d
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/155145


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>

This allows a better portability of the function.
Use write_cntfrq_el0 which can be used on both AARCH32 and AARCH64.
Add missing includes.

Change-Id: I1cbe9f58a33b90397c49b905daa561628ed3bfc2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

When coming back from standby, the backup value must be
restored with the sleep time.
Rework the function to add a backup counter value to be
added to the sleep time and move stgen functions to
stm32mp generic code.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I978a591a3a344561758117742b0dcdd862e1a6f0

This parameter "st,phy-cal" becomes optional and when it is
absent the built-in PHY calibration is done.

It is the case in the helper dtsi file "stm32mp15-ddr.dtsi"
except if DDR_PHY_CAL_SKIP is defined.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I38ffd4aeca88fd45819d4e7d20840465a8a8e9bf
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/151296


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

stm32mp1_round_opp_khz() finds the nearest frequency from the one provided,
without exceeding it. It parses static PLL1 settings structure to get it.

Change-Id: I99d92c742fb8166c5b76988518ab61077173edcc
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

stm32mp1_set_opp_khz() is the top-level service. It parses
internally the opp_table in Device Tree and applies the
PLL1 parameters.
Add also get/save functions to access to the current OPP
frequency, saved as static variable during clock driver probe.
Create dedicated services to compute pllxcfgr values.

Change-Id: I84ddc0c82af5ad7d0541e43061c800a98be4b9c7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Create a static structure containing, for each CPU operating point, the
corresponding VDDCORE voltage and all PLL1 settings.
All OPP PLL1 settings are computed during cold boot and saved in RAM.
stm32mp1_clk_lp_save/load_opp_pll1_settings() functions allow to manage
these settings in the context during the standby mode transitions.

clk_compute_pll1_settings() uses a simplified but optimized algorithm,
to compute PLL1 configuration and fractional values from the PLL12
input frequency, given by the Device Tree, and the expected CPU frequency.
clk_get_pll1_settings() just gets the input frequency before calling
the algorithm. If they have already been computed, structure is parsed.

A stm32mp1_clk_compute_all_pll1_settings() service gets frequency and
voltage information from OPP table, and fills PLL1 settings structure,
either by retrieving parameters in RCC registers (case of the current
values, managed by clk_save_current_pll1_settings() function), or by
computing them.

stm32mp1_clk_init() calls clk_get_pll1_settings() when a non-null CPU
expected frequency value is entered as new entry parameter, and when PLL1
settings are not hardly-defined in the Device Tree.

stm32mp1_clk_get_maxfreq_opp() parse OPP table in RAM to get OPP
coordinates (frequency value and VDDCORE voltage) corresponding to the
highest frequency couple.

Change-Id: I4dd84c56a1d834858621ec1ba9c1f35cfa0a59de
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

fdt_is_pll1_predefined() checks if PLL1 hard-coded settings
have been defined in DT.
It will determine if they have to be computed by the software.
This support aims at backward compatibility of the DT used in
stm32mp1 TF-A.

Change-Id: Ied5df27fab0ca32d93917f1d92f3f71988afb93d
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Saved timing and frequency values are related to a specific I2C instance,
they should be part of the handle structure.

Change-Id: Ib05dde7668201999c0b46bc5297cd5a2be307143
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Prepare new clock tree initialization scheme, by splitting PMIC
initialization in three phases.

initialize_pmic() configures the PMIC I2C link, and registers the PMIC
resource. It is called twice in BL2 stage: before clock tree
initialization to check VDDCORE voltage and update it if necessary, and
after to re-sync I2C link with new clock update. It is also used in BL32
stage.

configure_pmic() sets the boot_on configuration for all regulators. It is
used in BL2 only. Then, before PLLs and clock tree init, VDDCORE regulator
voltage update is possible if requested by the device tree configuration.

print_pmic_info_and_debug() prints the PMIC version ID and displays
regulator information if debug is enabled.

Change-Id: Ib81a625740b7ec6abb49cfca05e44c69efaa4718
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Do not limit to 3 (100KHz, 400KHz, 1MHz) bus frequencies, but instead
allow for any frequency up to 1MHz. Depending on the requested frequency
(via the clock-frequency DT entry), use the spec data from either
Standard, Fast or Fast Plus mode.

Change-Id: I23fea20465742e15f79f4c501e544cfc62611675
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/143784


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com>

The function stm32_i2c_get_setup_from_fdt() was using fdt_getprop() to
to get some i2c node properties, and set a default value if the node was
not found. The function fdt_read_uint32_default() already does this in
a simpler way. The void *fdt parameter is then useless.

Change-Id: I74c6295bb5765ee7c7e0a9ae020b741f1fe022a6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/143783


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com>

Improve use and readability.

Change-Id: Ia99fc38287f36c9dd12bfe51352afa5da68c0e47
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/142979


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Factorize DT information handling in a single static function.
This source code was reused several times, it renders it common.

In modified functions, align return code to avoid mixing between
ERRNO and FDT families.
Remove also dt_ prefix from functions if they do not only deal
with Device Tree, in that case ERRNO code is used.

Change-Id: I214acb1f8d50388636df9cb0cae64a6536e2376f
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

The wakeup from STOP mode should be available even if TZEN bit is 0 in RCC.

Change-Id: I4301ebf76d4a48972bfc2c3d14945a7c18249b51
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/138474


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com>
Tested-by: Lionel DEBIEVE <lionel.debieve@st.com>