Change-Id: I544654eadfb9bac86683c191ea69299612c8ec51
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Add FW_CONFIG device tree files for all boards. The file content is for
the moment common to all boards. It describes where the different images
will be loaded.

Change-Id: Id957b49b0117864136250bfc416664f815043ada
Signed-off-by: Yann Gautier <yann.gautier@st.com>

BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP file.
One DTB is created for each BL. To reduce their sizes, 2 new dtsi file are
in charge of removing useless nodes for a given BL. This is done because
BL2 and BL32 share the same device tree files base.

Change-Id: I1ffada0af58486d4cf6044511b51e56b52269817
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Change-Id: I0adb2c6bf21e840d6b795292357f3615361b767e
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Enable TRUSTED_BOARD_BOOT. This change removes calls to
stm32mp_check_header() and stm32mp_auth_image() when boot images
are loaded since images are now verified from the authentication
framework.

Change-Id: Iec5b645e1581543c99ae59bdb4dd033c577f2295
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

Change platform DTS and shared resources driver to ensure all
secureable peripherals of ETZPC is configured so that we can
check each configuration against resources assignation.

Change-Id: I66b75e990e1d3ba65aea6051811568fb2e5b02e2
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/153126


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

This parameter "st,phy-cal" becomes optional and when it is
absent the built-in PHY calibration is done.

It is the case in the helper dtsi file "stm32mp15-ddr.dtsi"
except if DDR_PHY_CAL_SKIP is defined.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I38ffd4aeca88fd45819d4e7d20840465a8a8e9bf
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/151296


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

PLL1 settings are now computed from OPP table frequencies.

Change-Id: Icc8ab3975cb5e1ef4ab14796868735d39d2e5d65
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Fix the following DT dtc warnings for stm32mp1 boards:

Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@0:
 node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@1:
 node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@2:
 node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@3:
 node has a unit name, but no reg property

Update device tree bindings documentation.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I91be408ea1d9b0474caf4965175df33792b7e11e

Align STPMIC1 configuration with linux.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I4efaa889fec4337ab2516daf17452f63f874a757
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/144883


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

No more used, "st,non-secure-otp" property replaces them.

Change-Id: Iacf3b547951e17503ba826b537c7deaf8a53dcd4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Avoid mixing dash and underscore.

Change-Id: I7f8b6c5397d789c3cb2fdbae50205610c5595af7
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Originally required for CubeMX.
Still the case?

Change-Id: Icab89afbdb4852821062fa00ffadc07aba39aea9

Change-Id: I81ceb6399e2f6067be42afc5192f00a497a399d9

Change-Id: I3511c88d174c7404da20910526427d096fce9241
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

Change-Id: I8e0ba794e5ded1290fb83fe8d43ce54d4dc0e320
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Set non-secure property on platform secure OTP nodes that non-secure world
is allowed to access through secure world services.
These are the SoC MAC address and the ST boards board_id OTPs.

Change-Id: Idfa6322d9d5c35285706d0b2d32ae09af38684a7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/138264


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list allows easy access to OTP offsets defined in BSEC node,
where more OTP definitions with offsets in bytes and length have
been added (replace hard-coded values).
Each board may redefine this list, especially for board_id info.

Change-Id: I910ae671b3bf3320ee6500fecc9ec335ae67bbda
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts

Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

Without this node, the board fails to boot and panics in the function
stm32mp_init_auth().

Change-Id: Ia54924410dac2a8c94dd6e45d7e93977fe7d87e2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.

Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

enable virtio-rng component for morello fvp platform

Change-Id: I89b950f067a4d14dfa418de3859c88c8f91cf7c5
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>

The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.

Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.

Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Change-Id: Ib5945c37983505f327a195bdb8b91ed1b7b90921
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A

The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.

There are 4 packages available, for which  the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.

STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.

Some reordering is done in other files, and realign with kernel DT files.

The DDR files are generated with our internal tool, no changes in the
registers values.

Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>

This is as part of the architecture change in TC0.

Change-Id: I470241f67938e7998941d26f0e8bc05073234152
Signed-off-by: Usama Arif <usama.arif@arm.com>

Remote chip  ITS, SMMU, PCIe nodes are added for enabling remote
chip PCIe hierarchy.

Change-Id: I5b3ca733715defa38e413588ccd13d0688cba271
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>

This change replaces hdlcd with DPU in dts file for TC0

Change-Id: If25dfd3ddffc07279ab487f65e1bb82b27a26604
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>

Add USB IP node as the MPS3 board has the NXP isp1763 host controller.

Change-Id: I47c57e4c8345d244c46895b52fcaecc1c6f1b504
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com>

Created a header file defining the id of the various nv-counters
used in the system.
Also, updated the device tree to add 'id' property for the trusted
and non-trusted nv-counters.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia41a557f7e56ad4ed536aee11c7a59e078ae07c0

This includes both cpu and cluster sleep parameters.

Change-Id: I6a9e90b88508d6d2acd2538007cbbdd1cf976442
Signed-off-by: Usama Arif <usama.arif@arm.com>

The pl180 mmc uses 3.3V fixed regulator and vexpress
sysreg for card detection and write protect.

Change-Id: I2513cfcb97217e282a081a700f3a9f723e8207ff
Signed-off-by: Usama Arif <usama.arif@arm.com>

Currently only single signing domain is supported for SP packages but
there is plan to support dual signing domains if CoT is dualroot.

SP_CONTENT_CERT_ID is the certificate file which is currently generated
and signed with trusted world key which in-turn is derived from Silicon
provider RoT key.
To allow dual signing domain for SP packages, other certificate file
will be derived from Platform owned RoT key.

This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and
does other related changes.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93

Provide manifest and build options to boot OP-TEE as a
guest S-EL1 Secure Partition on top of Hafnium in S-EL2.

Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb

N1SDP supports both single-chip and multi-chip environment.
Added  DTS file for both type of environment.
Enabled DTS files compilation for N1SDP platform.

Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0
Co-authored-by: Robin Murphy <Robin.Murphy@arm.com>
Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com>
Co-authored-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>

Added CoT descriptor nodes and properties in device tree.
Currently, CoT descriptors which are used by BL2 are added as part
of device tree.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Iff23cff843e5489fac18bcee5f5d6a71de5ad0d0

This patch performs the following:

- Creating two corstone700 platforms under corstone700 board:

  fvp and fpga

- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
  - Enabling NEED_BL33 option
  - Fixing non-secure image base: For no preloaded bl33 we want to
    have the NS base set on shared ram. Setup a memory map region
    for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY

Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

Using the fconf framework, the Group 0 and Group 1 secure interrupt
descriptors are moved to device tree and retrieved in runtime. This
feature is enabled by the build flag SEC_INT_DESC_IN_FCONF.

Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Fix etzpc node location in stm32mp157c DTSI file as requested during the
patch review. The comment was addressed then fixup change discarded while
rebasing.

Change-Id: Ie53531fec7da224de0b86c968a66aec441bfc25d
Fixes: 627298d4 ("dts: stm32mp157c: add etzpc node")
Reported-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Add a node for the ETZPC device so that driver initializes during
stm32mp15* boot sequence.

Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>