Varun Wadekar
authored
This patch adds a build config 'RAS_TRAP_LOWER_EL_ERR_ACCESS' to set
SCR_EL3.TERR during CPU boot. This bit enables trapping RAS register
accesses from EL1 or EL2 to EL3.
RAS_TRAP_LOWER_EL_ERR_ACCESS is disabled by default.
Signed-off-by: 
Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifb0fb0afedea7dd2a29a0b0491a1161ecd241438| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| tbbr | ||
| armv7-a-cpus.mk | ||
| build_env.mk | ||
| build_macros.mk | ||
| cygwin.mk | ||
| defaults.mk | ||
| msys.mk | ||
| plat_helpers.mk | ||
| unix.mk | ||
| windows.mk | ||