Create a static structure containing, for each CPU operating point, the
corresponding VDDCORE voltage and all PLL1 settings.
All OPP PLL1 settings are computed during cold boot and saved in RAM.
stm32mp1_clk_lp_save/load_opp_pll1_settings() functions allow to manage
these settings in the context during the standby mode transitions.

clk_compute_pll1_settings() uses a simplified but optimized algorithm,
to compute PLL1 configuration and fractional values from the PLL12
input frequency, given by the Device Tree, and the expected CPU frequency.
clk_get_pll1_settings() just gets the input frequency before calling
the algorithm. If they have already been computed, structure is parsed.

A stm32mp1_clk_compute_all_pll1_settings() service gets frequency and
voltage information from OPP table, and fills PLL1 settings structure,
either by retrieving parameters in RCC registers (case of the current
values, managed by clk_save_current_pll1_settings() function), or by
computing them.

stm32mp1_clk_init() calls clk_get_pll1_settings() when a non-null CPU
expected frequency value is entered as new entry parameter, and when PLL1
settings are not hardly-defined in the Device Tree.

stm32mp1_clk_get_maxfreq_opp() parse OPP table in RAM to get OPP
coordinates (frequency value and VDDCORE voltage) corresponding to the
highest frequency couple.

Change-Id: I4dd84c56a1d834858621ec1ba9c1f35cfa0a59de
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>