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riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs. Below are the blocks which are enabled: - CPG - CPU0 - DDR (memory regions) - PINCTRL - PLIC - SCIF0 As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and carrier [2] board DTSIs which enables almost all the blocks supported by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually enabling the blocks hence the aliases for ETH/I2C are deleted and rest of the IP blocks are marked as disabled/deleted. [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by:Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Acked-by:
Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- arch/riscv/boot/dts/Makefile 1 addition, 0 deletionsarch/riscv/boot/dts/Makefile
- arch/riscv/boot/dts/renesas/Makefile 2 additions, 0 deletionsarch/riscv/boot/dts/renesas/Makefile
- arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts 27 additions, 0 deletionsarch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
- arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi 58 additions, 0 deletionsarch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
- arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi 91 additions, 0 deletionsarch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
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