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perf/x86: Support counter mask
The current perf assumes that both GP and fixed counters are contiguous. But it's not guaranteed on newer Intel platforms or in a virtualization environment. Use the counter mask to replace the number of counters for both GP and the fixed counters. For the other ARCHs or old platforms which don't support a counter mask, using GENMASK_ULL(num_counter - 1, 0) to replace. There is no functional change for them. The interface to KVM is not changed. The number of counters still be passed to KVM. It can be updated later separately. Signed-off-by:Kan Liang <kan.liang@linux.intel.com> Signed-off-by:
Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by:
Andi Kleen <ak@linux.intel.com> Reviewed-by:
Ian Rogers <irogers@google.com> Link: https://lkml.kernel.org/r/20240626143545.480761-3-kan.liang@linux.intel.com
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- arch/x86/events/amd/core.c 12 additions, 12 deletionsarch/x86/events/amd/core.c
- arch/x86/events/core.c 47 additions, 51 deletionsarch/x86/events/core.c
- arch/x86/events/intel/core.c 80 additions, 84 deletionsarch/x86/events/intel/core.c
- arch/x86/events/intel/ds.c 8 additions, 11 deletionsarch/x86/events/intel/ds.c
- arch/x86/events/intel/knc.c 1 addition, 1 deletionarch/x86/events/intel/knc.c
- arch/x86/events/intel/p4.c 5 additions, 5 deletionsarch/x86/events/intel/p4.c
- arch/x86/events/intel/p6.c 1 addition, 1 deletionarch/x86/events/intel/p6.c
- arch/x86/events/perf_event.h 39 additions, 8 deletionsarch/x86/events/perf_event.h
- arch/x86/events/zhaoxin/core.c 6 additions, 6 deletionsarch/x86/events/zhaoxin/core.c
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