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riscv: Add Zawrs support for spinlocks
RISC-V code uses the generic ticket lock implementation, which calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). Introduce a RISC-V specific implementation of smp_cond_load_relaxed() which applies WRS.NTO of the Zawrs extension in order to reduce power consumption while waiting and allows hypervisors to enable guests to trap while waiting. smp_cond_load_acquire() doesn't need a RISC-V specific implementation as the generic implementation is based on smp_cond_load_relaxed() and smp_acquire__after_ctrl_dep() sufficiently provides the acquire semantics. This implementation is heavily based on Arm's approach which is the approach Andrea Parri also suggested. The Zawrs specification can be found here: https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc Signed-off-by:Christoph Müllner <christoph.muellner@vrull.eu> Co-developed-by:
Andrew Jones <ajones@ventanamicro.com> Signed-off-by:
Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20240426100820.14762-11-ajones@ventanamicro.com Signed-off-by:
Palmer Dabbelt <palmer@rivosinc.com>
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- arch/riscv/Kconfig 13 additions, 0 deletionsarch/riscv/Kconfig
- arch/riscv/include/asm/barrier.h 30 additions, 15 deletionsarch/riscv/include/asm/barrier.h
- arch/riscv/include/asm/cmpxchg.h 58 additions, 0 deletionsarch/riscv/include/asm/cmpxchg.h
- arch/riscv/include/asm/hwcap.h 1 addition, 0 deletionsarch/riscv/include/asm/hwcap.h
- arch/riscv/include/asm/insn-def.h 2 additions, 0 deletionsarch/riscv/include/asm/insn-def.h
- arch/riscv/kernel/cpufeature.c 1 addition, 0 deletionsarch/riscv/kernel/cpufeature.c
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