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Commit be2a8c47 authored by Kornel Dulęba's avatar Kornel Dulęba Committed by Frieder Schrempf
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Revert "pinctrl: amd: Disable and mask interrupts on resume"


commit 534e4658 upstream.

This reverts commit b26cd932.

This patch introduces a regression on Lenovo Z13, which can't wake
from the lid with it applied; and some unspecified AMD based Dell
platforms are unable to wake from hitting the power button

Signed-off-by: default avatarKornel Dulęba <korneld@chromium.org>
Reviewed-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230411134932.292287-1-korneld@chromium.org


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent eed5f45d
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1 merge request!117Revert "pinctrl: amd: Disable and mask interrupts on resume"
...@@ -775,34 +775,31 @@ static const struct pinconf_ops amd_pinconf_ops = { ...@@ -775,34 +775,31 @@ static const struct pinconf_ops amd_pinconf_ops = {
.pin_config_group_set = amd_pinconf_group_set, .pin_config_group_set = amd_pinconf_group_set,
}; };
static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, u32 pin) static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
{ {
const struct pin_desc *pd; struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
unsigned long flags; unsigned long flags;
u32 pin_reg, mask; u32 pin_reg, mask;
int i;
mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
BIT(WAKE_CNTRL_OFF_S4); BIT(WAKE_CNTRL_OFF_S4);
pd = pin_desc_get(gpio_dev->pctrl, pin); for (i = 0; i < desc->npins; i++) {
if (!pd) int pin = desc->pins[i].number;
return; const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
raw_spin_lock_irqsave(&gpio_dev->lock, flags); if (!pd)
pin_reg = readl(gpio_dev->base + pin * 4); continue;
pin_reg &= ~mask;
writel(pin_reg, gpio_dev->base + pin * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) raw_spin_lock_irqsave(&gpio_dev->lock, flags);
{
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
int i;
for (i = 0; i < desc->npins; i++) { pin_reg = readl(gpio_dev->base + i * 4);
amd_gpio_irq_init_pin(gpio_dev, desc->pins[i].number); pin_reg &= ~mask;
writel(pin_reg, gpio_dev->base + i * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
} }
} }
...@@ -856,10 +853,8 @@ static int amd_gpio_resume(struct device *dev) ...@@ -856,10 +853,8 @@ static int amd_gpio_resume(struct device *dev)
for (i = 0; i < desc->npins; i++) { for (i = 0; i < desc->npins; i++) {
int pin = desc->pins[i].number; int pin = desc->pins[i].number;
if (!amd_gpio_should_save(gpio_dev, pin)) { if (!amd_gpio_should_save(gpio_dev, pin))
amd_gpio_irq_init_pin(gpio_dev, pin);
continue; continue;
}
raw_spin_lock_irqsave(&gpio_dev->lock, flags); raw_spin_lock_irqsave(&gpio_dev->lock, flags);
gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
......
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