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Alexander Arndt
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Andreas Findeklee afindeklee
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Annette Kobou akobou
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Armin Mück amueck
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Daniel Ehrler dehrler
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Devran Ölcer doelcer
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Dieter Scheufele dscheufele
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Dietmar Kolbus dkolbus
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Dominik Wurster Wurster
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Eberhard Stoll estoll
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Florian Mayer fmayer
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Frieder Schrempf
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Julian Bauknecht jbauknecht
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Jó Bitsch jbitsch
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Jürgen Kling
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Klemenz Christof kchristof
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Lukas Loosli lloosli
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Marc Gonser mgonser
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Markus Abegg mabegg
- May 30, 2019
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Maxime Ripard authored
The Allwinner SoCs have a MIPI-DSI and MIPI-D-PHY controllers supported in Linux, with a matching Device Tree binding. Now that we have the DT validation in place, let's convert the device tree bindings for that controller over to a YAML schemas. Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by:
Chen-Yu Tsai <wens@csie.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190527120910.18964-1-maxime.ripard@bootlin.com
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- Jan 25, 2019
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Chen-Yu Tsai authored
The A23's display pipeline is similar to the A33. Differences include: - Display backend supports larger layers, 8192x8192 instead of 2048x2048 - TCON has DMA input - There is no SAT module packed in the display backend Add compatible strings for the display pipeline and its components. As the MIPI DSI output device is not officially documented, and there are no A23 reference devices to test it, it is not covered by this patch. Signed-off-by:
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- Nov 05, 2018
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Icenowy Zheng authored
Allwinner H6 SoC has a cut down version of TCON TOP. Add binding documentation for it. Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> [expanded description] Signed-off-by:
Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by:
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Icenowy Zheng authored
The Allwinner H6 SoC uses a v2.12a DesignWare HDMI controller, with dedicated CEC and HDCP clocks added; the PHY connected is a standard DesignWare HDMI PHY. Add binding for it. Reviewed-by:
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Jernej Skrabec authored
This commit adds compatibles used in H6 display pipeline, namely for display engine, mixer and TV TCON. H6 display engine is somewhat similar to R40, just less TCONs and mixer support more features. Reviewed-by:
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- Sep 27, 2018
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Jernej Skrabec authored
R40 DE2 mixers are similar to those found in A83T, except it needs different clock settings. Add a compatibles for them. Reviewed-by:
Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-14-jernej.skrabec@siol.net
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- Sep 19, 2018
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Icenowy Zheng authored
The Allwinner R40 HDMI PHY is currently the only one that seems to be able to select between two PLL inputs. Add a compatible string for it, and the pll-1 clock input definition. Signed-off-by:
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- Sep 05, 2018
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Icenowy Zheng authored
Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC" pin, which is the VCC of HDMI part. Add a supply property to specify HVCC's regulator in the device tree. Signed-off-by:
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Jagan Teki authored
The HDMI controller on Allwinner A64 is similar on the one on H3/H5/A83T (although the PHY is different with A83T). Add A64 compatible and append A83T compatible as fallback. Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Reviewed-by:
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Jagan Teki authored
Allwinner A64 has a DE2 display pipeline. The TCONs are similar to the ones in A83T, but the mixers are new (similar to the later R40 SoC). This patch adds dt-binding documentation for A64 DE2 display pipeline. Signed-off-by:
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- Jul 11, 2018
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Jernej Skrabec authored
They are currently sorted alphabetically. However, they should be sorted by release date of the family and then alphabetically. Fixes: 03c35dbf ("dt-bindings: display: sun4i-drm: Add description of A64 HDMI PHY") Reviewed-by:
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Jernej Skrabec authored
TCON description is expanded with R40 TV TCON compatible. It is a bit special, because it is connected to TCON TOP instead directly to mixer and it needs special handling. Reviewed-by:
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Jernej Skrabec authored
R40 has pretty unique display pipeline. It supports two outputs at the same time. Possible outputs: - 1x HDMI, - 2x TV output - 1x VGA, - 1x MIPI DSI and - 2x LCD outputs That is the biggest number of possible outputs from all Allwinner SoC. Because of that, add new compatible for it. Reviewed-by:
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- Jun 27, 2018
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Jernej Skrabec authored
A64 HDMI PHY is similar to H3 HDMI PHY except it has two possible PLL clock parents. It is compatible to other HDMI PHYs, like that found in R40. Acked-by:
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Jernej Skrabec authored
TCON TOP main purpose is to configure whole display pipeline. It determines relationships between mixers and TCONs, selects source TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV encoder clock source and contains additional TV TCON and DSI gates. Reviewed-by:
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- Apr 11, 2018
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Maxime Ripard authored
The Allwinner SoCs usually come with a DSI encoder. Add a binding for it. Reviewed-by:
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- Mar 19, 2018
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Chen-Yu Tsai authored
This patch adds compatible strings for the remaining documented components of the Allwinner A80 display pipeline. Reviewed-by:
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Chen-Yu Tsai authored
The display pipeline on the A80 SoC has what is called the Detail Enhancement Unit, or DEU for short, block in between the display frontend and backend. This unit can sharpen images in both luma and chroma channels. It seems to also do colorspace conversion. This patch adds the device tree binding for this hardware block. Reviewed-by:
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Chen-Yu Tsai authored
The A80 has 2 or 3 TCONs. The documentation and vendor kernel are very vague about the third TCON, to the point that it might not exist. In the documentation, the first TCON is missing channel 1, and the second is missing channel 0. However the vendor kernel seems to be able to use them regardless. Here we model them like the old TCONs. An oddity is that TCON0 requires the reset control for the eDP block to be deasserted, for any register access to stick. This patch adds compatible strings for TCON0 and TCON1, with TCON0 requiring an extra "edp" reset control. Reviewed-by:
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- Mar 02, 2018
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Jernej Skrabec authored
Add missing compatibles for H3 HDMI pipeline. These compatibles can also be used with H5 SoC. Signed-off-by:
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- Feb 16, 2018
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Jernej Skrabec authored
This commit adds all necessary compatibles and descriptions needed to implement A83T HDMI pipeline. Mixer is already properly described, so only compatible is added. However, A83T TV TCON, which is connected to HDMI, doesn't have channel 0, contrary to all TCONs currently described. Because of that, TCON documentation is extended. A83T features Synopsys DW HDMI controller with a custom PHY which looks like Synopsys Gen2 PHY with few additions. Since there is no documentation, needed properties were found out through experimentation and reading BSP code. At the end, example is added for newer SoCs, which feature DE2 and DW HDMI. Signed-off-by:
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- Jan 04, 2018
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Maxime Ripard authored
The A83T has two video pipelines in parallel that looks quite similar to the other SoCs. The video planes are handled through a controller called the mixer, and the video signal is then passed to the timing controller (TCON). And while there is two instances of the mixers and TCONs, they have a significant number of differences. The TCONs are quite easy to deal with, one is supposed to generate TV (in the broader term, so including things like HDMI) signals, the other one LCD (so RGB, LVDS, DSI) signals. And while they are called TCON0 and TCON1 in the A83t datasheet, newer SoCs call them TCON-TV and TCON-LCD, which seems more appropriate. However, the mixers differ mostly by their capabilities, with some features being available only in the first one, or the number of planes they expose, but also through their register layout. And while the capabilities could be represented as properties, the register layout differences would need to express all the registers offsets as properties, which is usually quite bad. Especially since documentation on that hardware block is close to non-existent and we don't even have the list of all those registers in the first place. So let's call them mixer 0 and 1 in our compatibles, even though the name is pretty bad... At the moment, we only have tested the code on a board that has a single display output, so we're leaving the tcon-tv and mixer1 out. Reviewed-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Link: https://patchwork.freedesktop.org/patch/msgid/2702a5c1d224af1c51743492ad1b917966f2ad43.1513854122.git-series.maxime.ripard@free-electrons.com
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Maxime Ripard authored
Some clocks and resets supposed to drive the LVDS logic in the display engine have been overlooked when the driver was first introduced. Add those additional resources to the binding, and we'll deal with the ABI stability in the code. Reviewed-by:
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- Nov 09, 2017
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Marco Franchi authored
Improve the binding example by removing all the leading zeros to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading 0s Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find ./Documentation/devicetree/bindings "*.txt"` Some unnecessary changes were manually fixed. Signed-off-by:
Marco Franchi <marco.franchi@nxp.com> Signed-off-by:
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- Oct 17, 2017
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Jonathan Liu authored
The A20 display pipeline has 2 frontends, 2 backends, and 2 TCONs. This patch adds support (or a compatible string in the frontend's case) for these components. The TCONs support directly outputting to CPU/RGB/LVDS LCD panels, or it can output to HDMI via an on-chip HDMI controller, or CVBS/YPbPr/VGA signals via on-chip TV encoders. These additional encoders are not covered in this patch. Signed-off-by:
Jonathan Liu <net147@gmail.com> [wens@csie.org: Expand commit message] Signed-off-by:
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Chen-Yu Tsai authored
The A10 display pipeline has 2 frontends, 2 backends, and 2 TCONs. This patch adds support (or a compatible string in the frontend's case) for these components. The TCONs support directly outputting to CPU/RGB/LVDS LCD panels, or it can output to HDMI via an on-chip HDMI controller, or CVBS/YPbPr/VGA signals via on-chip TV encoders. These additional encoders are not covered in this patch. Signed-off-by:
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Chen-Yu Tsai authored
The HDMI controller in the A10 SoC is the same as the one currently supported in the A10s. It has slightly different setup parameters. Since these parameters are not thoroughly understood, we add support for this variant by copying these parameters verbatim. Signed-off-by:
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Jonathan Liu authored
The A10 has two TCONs that are similar to the ones found on other SoCs. Like the A31, TCON0 has a register used to mux the TCON outputs to the downstream encoders. The bit fields are slightly different. Signed-off-by:
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- Oct 11, 2017
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Chen-Yu Tsai authored
The HDMI controller in the A31 SoC is slightly different from the earlier version. In addition to the TMDS clock and DDC controls, this version now takes a second DDC clock input. Add a compatible string for it, and add the DDC clock input to the list of clocks required. Signed-off-by:
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- Sep 05, 2017
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Rob Herring authored
Pretty much any node can have a status property, so it doesn't need to be in examples. Converted with the following command and removed examples with SoC and board specific splits: git grep -l -E 'status.*=.*' Documentation/devicetree/ | xargs sed -i -E '/\sstatus.*=.*"(disabled|ok|okay)/d' Acked-by:
Mark Rutland <mark.rutland@arm.com> Signed-off-by:
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- Jul 18, 2017
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Chen-Yu Tsai authored
The explanation for the endpoint ID numbering scheme is convoluted and hard to understand. This patch aims to improve the readability of it by combining the existing two paragraphs, while also providing a diagram example, and how endpoints should be numbered based on that example. Signed-off-by:
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- Jun 01, 2017
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Maxime Ripard authored
The A10s has a slightly different display pipeline than the A13, with an HDMI controller. Add a compatible for it. Reviewed-by:
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Maxime Ripard authored
The Allwinner Timings Controller has two, mutually exclusive, channels. When the binding has been introduced, it was assumed that there would be only a single user per channel in the system. While this is likely for the channel 0 which only connects to LCD displays, it turns out that the channel 1 can be connected to multiple controllers in the SoC (HDMI and TV encoders for example). And while the simultaneous use of HDMI and TV outputs cannot be achieved, switching from one to the other at runtime definitely sounds plausible. Add an extra property, allwinner,tcon-channel, to specify for a given endpoint which TCON channel it is connected to, while falling back to the previous mechanism if that property is missing. Acked-by:
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Maxime Ripard authored
One of the possible output of the display pipeline, on the SoCs that have it, is the HDMI controller. Add a binding for it. Acked-by:
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- May 15, 2017
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Icenowy Zheng authored
Allwinner V3s SoC have a display engine which have a different pipeline with older SoCs. Add document for it (new compatibles and the new "mixer" part). Signed-off-by:
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- May 14, 2017
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Chen-Yu Tsai authored
The Allwinner display pipeline contains many hardware components, some of which can consume data from one of multiple upstream components. The numbering scheme of these components must be encoded into the device tree so the driver can figure out which component out of two or more of the same type it is supposed to use or program. This patch adds the constraint that local endpoint IDs must be the index or number of the remote endpoint's hardware block, for all components in the display pipeline up to the TCONs. Signed-off-by:
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- Mar 29, 2017
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Chen-Yu Tsai authored
The display backend has an interrupt line. Add it to the device tree binding. Signed-off-by:
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- Oct 20, 2016
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Chen-Yu Tsai authored
The A31's display pipeline has 2 frontends, 2 backends, and 2 TCONs. It also has new display enhancement blocks, such as the DRC (Dynamic Range Controller), the DEU (Display Enhancement Unit), and the CMU (Color Management Unit). It supports HDMI, MIPI DSI, and 2 LCD/LVDS channels. The A31s display pipeline is almost the same, just without MIPI DSI. Only the TCON seems to be different, due to the missing mux for MIPI DSI. Add compatible strings for both of them. Signed-off-by:
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Chen-Yu Tsai authored
The A31 TCON has mux controls for how TCON outputs are routed to the HDMI and MIPI DSI blocks. Since the A31s does not have MIPI DSI, it only has a mux for the HDMI controller input. This patch only adds support for the compatible strings. Actual support for the mux controls should be added with HDMI and MIPI DSI support. Signed-off-by:
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Chen-Yu Tsai authored
The A31 and A31s also have the DRC as part of the display pipeline. As we know virtually nothing about them, just add compatible strings for both SoCs to the stub driver. Signed-off-by:
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