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Commit 05d54b82 authored by Fabio Estevam's avatar Fabio Estevam Committed by Stefano Babic
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mx6: Add support for the mx6solox variant 


mx6solox is the newest member of the mx6 family.

Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual Gigabit Ethernet

Add the initial support for it.

Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
parent e153333e
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with 369 additions and 7 deletions
arch/arm/cpu/armv7/mx6/clock.c
+ 2
− 2
View file @ 05d54b82
......@@ -214,7 +214,7 @@ static u32 get_uart_clk(void)
u32 reg, uart_podf;
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
#ifdef CONFIG_MX6SL
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
freq = MXC_HCLK;
#endif
......@@ -282,7 +282,7 @@ static u32 get_emi_slow_clk(void)
return root_freq / (emi_slow_podf + 1);
}
#ifdef CONFIG_MX6SL
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
......
arch/arm/cpu/armv7/mx6/soc.c
+ 26
− 0
View file @ 05d54b82
......@@ -79,9 +79,15 @@ u32 __weak get_board_rev(void)
void init_aips(void)
{
struct aipstz_regs *aips1, *aips2;
#ifdef CONFIG_MX6SX
struct aipstz_regs *aips3;
#endif
aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
#ifdef CONFIG_MX6SX
aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
#endif
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
......@@ -107,6 +113,26 @@ void init_aips(void)
writel(0x00000000, &aips2->opacr2);
writel(0x00000000, &aips2->opacr3);
writel(0x00000000, &aips2->opacr4);
#ifdef CONFIG_MX6SX
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, &aips3->mprot0);
writel(0x77777777, &aips3->mprot1);
/*
* Set all OPACRx to be non-bufferable, not require
* supervisor privilege level for access,allow for
* write access and untrusted master access.
*/
writel(0x00000000, &aips3->opacr0);
writel(0x00000000, &aips3->opacr1);
writel(0x00000000, &aips3->opacr2);
writel(0x00000000, &aips3->opacr3);
writel(0x00000000, &aips3->opacr4);
#endif
}
static void clear_ldo_ramp(void)
......
arch/arm/imx-common/cpu.c
+ 2
− 0
View file @ 05d54b82
......@@ -112,6 +112,8 @@ const char *get_imx_type(u32 imxtype)
return "6SOLO"; /* Solo version of the mx6 */
case MXC_CPU_MX6SL:
return "6SL"; /* Solo-Lite version of the mx6 */
case MXC_CPU_MX6SX:
return "6SX"; /* SoloX version of the mx6 */
case MXC_CPU_MX51:
return "51";
case MXC_CPU_MX53:
......
arch/arm/include/asm/arch-imx/cpu.h
+ 2
− 1
View file @ 05d54b82
......@@ -8,6 +8,7 @@
#define MXC_CPU_MX53 0x53
#define MXC_CPU_MX6SL 0x60
#define MXC_CPU_MX6DL 0x61
#define MXC_CPU_MX6SOLO 0x62
#define MXC_CPU_MX6SX 0x62
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6D 0x64
#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
arch/arm/include/asm/arch-mx6/crm_regs.h
+ 170
− 0
View file @ 05d54b82
This diff is collapsed.
arch/arm/include/asm/arch-mx6/imx-regs.h
+ 118
− 4
View file @ 05d54b82
......@@ -19,6 +19,19 @@
#define GPU_2D_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define OPENVG_ARB_END_ADDR 0x02207FFF
#elif CONFIG_MX6SX
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00107FFF
#define GPU_ARB_BASE_ADDR 0x01800000
#define GPU_ARB_END_ADDR 0x01803FFF
#define APBH_DMA_ARB_BASE_ADDR 0x01804000
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
#else
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF
......@@ -39,14 +52,27 @@
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
#ifdef CONFIG_MX6SL
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
#define GPV2_BASE_ADDR 0x00D00000
#else
#define GPV2_BASE_ADDR 0x00200000
#endif
#ifdef CONFIG_MX6SX
#define GPV3_BASE_ADDR 0x00E00000
#define GPV4_BASE_ADDR 0x00F00000
#define GPV5_BASE_ADDR 0x01000000
#define GPV6_BASE_ADDR 0x01100000
#define PCIE_ARB_BASE_ADDR 0x08000000
#define PCIE_ARB_END_ADDR 0x08FFFFFF
#else
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
#define PCIE_ARB_BASE_ADDR 0x01000000
#define PCIE_ARB_END_ADDR 0x01FFFFFF
#endif
#define IRAM_BASE_ADDR 0x00900000
#define SCU_BASE_ADDR 0x00A00000
#define IC_INTERFACES_BASE_ADDR 0x00A00100
......@@ -56,13 +82,21 @@
#define L2_PL310_BASE 0x00A02000
#define GPV0_BASE_ADDR 0x00B00000
#define GPV1_BASE_ADDR 0x00C00000
#define PCIE_ARB_BASE_ADDR 0x01000000
#define PCIE_ARB_END_ADDR 0x01FFFFFF
#define AIPS1_ARB_BASE_ADDR 0x02000000
#define AIPS1_ARB_END_ADDR 0x020FFFFF
#define AIPS2_ARB_BASE_ADDR 0x02100000
#define AIPS2_ARB_END_ADDR 0x021FFFFF
#ifdef CONFIG_MX6SX
#define AIPS3_BASE_ADDR 0x02200000
#define AIPS3_END_ADDR 0x022FFFFF
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI1_ARB_BASE_ADDR 0x60000000
#define QSPI1_ARB_END_ADDR 0x6FFFFFFF
#define QSPI2_ARB_BASE_ADDR 0x70000000
#define QSPI2_ARB_END_ADDR 0x7FFFFFFF
#else
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
......@@ -75,8 +109,9 @@
#define IPU2_ARB_END_ADDR 0x02BFFFFF
#define WEIM_ARB_BASE_ADDR 0x08000000
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
#endif
#ifdef CONFIG_MX6SL
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
......@@ -88,8 +123,10 @@
#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
#endif
#ifndef CONFIG_MX6SX
#define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
#define IPU_SOC_OFFSET 0x00200000
#endif
/* Defines for Blocks connected via AIPS (SkyBlue) */
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
......@@ -112,7 +149,9 @@
#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
#else
#ifndef CONFIG_MX6SX
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#endif
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
......@@ -121,8 +160,10 @@
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
#endif
#ifndef CONFIG_MX6SX
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
#endif
#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
......@@ -157,6 +198,13 @@
#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#elif CONFIG_MX6SX
#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
#else
#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
......@@ -193,6 +241,8 @@
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
#ifdef CONFIG_MX6SL
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#elif CONFIG_MX6SX
#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#else
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#endif
......@@ -202,13 +252,28 @@
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#ifdef CONFIG_MX6SX
#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#else
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#endif
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
#ifdef CONFIG_MX6SX
#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#else
#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#endif
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#ifdef CONFIG_MX6SX
#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#else
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#endif
#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
......@@ -216,10 +281,42 @@
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#ifdef CONFIG_MX6SX
#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
#endif
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_5 0x15
#ifndef CONFIG_MX6SX
#define IRAM_SIZE 0x00040000
#else
#define IRAM_SIZE 0x00020000
#endif
#define FEC_QUIRK_ENET_MAC
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
......@@ -473,6 +570,22 @@ struct fuse_bank0_regs {
u32 rsvd7[4];
};
#ifdef CONFIG_MX6SX
struct fuse_bank4_regs {
u32 sjc_resp_low;
u32 rsvd0[3];
u32 sjc_resp_high;
u32 rsvd1[3];
u32 mac_addr_low;
u32 rsvd2[3];
u32 mac_addr_high;
u32 rsvd3[3];
u32 mac_addr2;
u32 rsvd4[7];
u32 gp1;
u32 rsvd5[7];
};
#else
struct fuse_bank4_regs {
u32 sjc_resp_low;
u32 rsvd0[3];
......@@ -487,6 +600,7 @@ struct fuse_bank4_regs {
u32 gp2;
u32 rsvd5[3];
};
#endif
struct aipstz_regs {
u32 mprot0;
......
arch/arm/include/asm/arch-mx6/mx6-ddr.h
+ 4
− 0
View file @ 05d54b82
......@@ -13,7 +13,11 @@
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#include "mx6dl-ddr.h"
#else
#ifdef CONFIG_MX6SX
#include "mx6sx-ddr.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6SX */
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
#else
......
arch/arm/include/asm/arch-mx6/mx6sx-ddr.h 0 → 100644
+ 45
− 0
View file @ 05d54b82
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX6SX_DDR_H__
#define __ASM_ARCH_MX6SX_DDR_H__
#ifndef CONFIG_MX6SX
#error "wrong CPU"
#endif
#define MX6_IOM_DRAM_DQM0 0x020e02ec
#define MX6_IOM_DRAM_DQM1 0x020e02f0
#define MX6_IOM_DRAM_DQM2 0x020e02f4
#define MX6_IOM_DRAM_DQM3 0x020e02f8
#define MX6_IOM_DRAM_RAS 0x020e02fc
#define MX6_IOM_DRAM_CAS 0x020e0300
#define MX6_IOM_DRAM_SDODT0 0x020e0310
#define MX6_IOM_DRAM_SDODT1 0x020e0314
#define MX6_IOM_DRAM_SDBA2 0x020e0320
#define MX6_IOM_DRAM_SDCKE0 0x020e0324
#define MX6_IOM_DRAM_SDCKE1 0x020e0328
#define MX6_IOM_DRAM_SDCLK_0 0x020e032c
#define MX6_IOM_DRAM_RESET 0x020e0340
#define MX6_IOM_DRAM_SDQS0 0x020e0330
#define MX6_IOM_DRAM_SDQS1 0x020e0334
#define MX6_IOM_DRAM_SDQS2 0x020e0338
#define MX6_IOM_DRAM_SDQS3 0x020e033c
#define MX6_IOM_GRP_ADDDS 0x020e05f4
#define MX6_IOM_DDRMODE_CTL 0x020e05f8
#define MX6_IOM_GRP_DDRPKE 0x020e05fc
#define MX6_IOM_GRP_DDRMODE 0x020e0608
#define MX6_IOM_GRP_B0DS 0x020e060c
#define MX6_IOM_GRP_B1DS 0x020e0610
#define MX6_IOM_GRP_CTLDS 0x020e0614
#define MX6_IOM_GRP_DDR_TYPE 0x020e0618
#define MX6_IOM_GRP_B2DS 0x020e061c
#define MX6_IOM_GRP_B3DS 0x020e0620
#endif /*__ASM_ARCH_MX6SX_DDR_H__ */
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