Support for multiple SGMII/TBI interfaces for TSEC ethernet

Fix TBI PHY accesses to use the proper offset in CPU register space. The
previous code would incorrectly access the TBI PHY by reading/writing to CPU
register space at the same location as would be used to access external PHYs.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>