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Commit c27c5e65 authored by Eberhard Stoll's avatar Eberhard Stoll
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stm32mp-t1000-k: Update CubeIDE project 

Update CubeIDE project to version 1.7.0 for dunfell support
parent be674f02
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conf/machine/cubemx/t1000-k/DeviceTree/t1000-k/kernel/stm32mp157c-t1000-k-mx.dts → conf/machine/cubemx/t1000-k/CA7/DeviceTree/t1000-k/kernel/stm32mp157c-t1000-k-mx.dts
+ 123
− 52
View file @ c27c5e65
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* /*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics. * Author: STM32CubeMX code generation for STMicroelectronics.
*/ */
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/dts-v1/; /dts-v1/;
#include "stm32mp157c.dtsi" #include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include "stm32mp157c-m4-srm.dtsi"
#include "stm32mp157cad-pinctrl.dtsi" #include "stm32mp157.dtsi"
#include "stm32mp15xc.dtsi"
#include "stm32mp15xxad-pinctrl.dtsi"
#include "stm32mp15-m4-srm.dtsi"
/* USER CODE BEGIN includes */ /* USER CODE BEGIN includes */
/* USER CODE END includes */ /* USER CODE END includes */
/ { / {
model = "STMicroelectronics custom STM32CubeMX board"; model = "STMicroelectronics custom STM32CubeMX board - openstlinux-5.10-dunfell-mp1-21-03-31";
compatible = "st,stm32mp157c-t1000-k-mx", "st,stm32mp157"; compatible = "st,stm32mp157c-t1000-k-mx", "st,stm32mp157";
memory@c0000000 { memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>; reg = <0xc0000000 0x20000000>;
/* USER CODE BEGIN memory */ /* USER CODE BEGIN memory */
...@@ -30,11 +38,6 @@ ...@@ -30,11 +38,6 @@
/* USER CODE BEGIN reserved-memory */ /* USER CODE BEGIN reserved-memory */
/* USER CODE END reserved-memory */ /* USER CODE END reserved-memory */
gpu_reserved: gpu@dc000000 {
reg = <0xdc000000 0x4000000>;
no-map;
};
}; };
/* USER CODE BEGIN root */ /* USER CODE BEGIN root */
...@@ -44,21 +47,23 @@ ...@@ -44,21 +47,23 @@
/* USER CODE BEGIN clocks */ /* USER CODE BEGIN clocks */
/* USER CODE END clocks */ /* USER CODE END clocks */
#ifndef CONFIG_TFABOOT
clk_lsi: clk-lsi {
clock-frequency = <32000>;
};
clk_hsi: clk-hsi { clk_hsi: clk-hsi {
clock-frequency = <64000000>; clock-frequency = <64000000>;
}; };
clk_csi: clk-csi { clk_csi: clk-csi {
clock-frequency = <4000000>; clock-frequency = <4000000>;
}; };
clk_lse: clk-lse { clk_lse: clk-lse {
clock-frequency = <32768>; clock-frequency = <32768>;
}; };
clk_hse: clk-hse { clk_hse: clk-hse {
clock-frequency = <24000000>; clock-frequency = <24000000>;
}; };
#endif /*CONFIG_TFABOOT*/
}; };
}; /*root*/ }; /*root*/
...@@ -82,10 +87,14 @@ ...@@ -82,10 +87,14 @@
eth1_pins_mx: eth1_mx-0 { eth1_pins_mx: eth1_mx-0 {
pins1 { pins1 {
pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */ pinmux = <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
<STM32_PINMUX('B', 12, AF11)>, /* ETH1_TXD0 */
<STM32_PINMUX('B', 13, AF11)>, /* ETH1_TXD1 */
<STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
<STM32_PINMUX('G', 8, AF2)>; /* ETH1_CLK */
bias-disable; bias-disable;
drive-push-pull; drive-push-pull;
slew-rate = <0>; slew-rate = <1>;
}; };
pins2 { pins2 {
pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */ pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */
...@@ -96,15 +105,6 @@ ...@@ -96,15 +105,6 @@
pins3 { pins3 {
pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */ pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */
}; };
pins4 {
pinmux = <STM32_PINMUX('B', 12, AF11)>, /* ETH1_TXD0 */
<STM32_PINMUX('B', 13, AF11)>, /* ETH1_TXD1 */
<STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */
<STM32_PINMUX('G', 8, AF2)>; /* ETH1_CLK */
bias-disable;
drive-push-pull;
slew-rate = <1>;
};
}; };
eth1_sleep_pins_mx: eth1_sleep_mx-0 { eth1_sleep_pins_mx: eth1_sleep_mx-0 {
...@@ -145,7 +145,7 @@ ...@@ -145,7 +145,7 @@
pins { pins {
pinmux = <STM32_PINMUX('D', 7, AF4)>, /* I2C2_SCL */ pinmux = <STM32_PINMUX('D', 7, AF4)>, /* I2C2_SCL */
<STM32_PINMUX('G', 15, AF4)>; /* I2C2_SDA */ <STM32_PINMUX('G', 15, AF4)>; /* I2C2_SDA */
bias-disable; bias-pull-up;
drive-open-drain; drive-open-drain;
slew-rate = <0>; slew-rate = <0>;
}; };
...@@ -162,7 +162,7 @@ ...@@ -162,7 +162,7 @@
pins { pins {
pinmux = <STM32_PINMUX('B', 7, AF6)>, /* I2C4_SDA */ pinmux = <STM32_PINMUX('B', 7, AF6)>, /* I2C4_SDA */
<STM32_PINMUX('E', 2, AF4)>; /* I2C4_SCL */ <STM32_PINMUX('E', 2, AF4)>; /* I2C4_SCL */
bias-disable; bias-pull-up;
drive-open-drain; drive-open-drain;
slew-rate = <0>; slew-rate = <0>;
}; };
...@@ -268,18 +268,12 @@ ...@@ -268,18 +268,12 @@
<STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */ <STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */
<STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */ <STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */
<STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */ <STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>; /* QUADSPI_BK1_IO1 */ <STM32_PINMUX('F', 9, AF10)>, /* QUADSPI_BK1_IO1 */
<STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
bias-disable; bias-disable;
drive-push-pull; drive-push-pull;
slew-rate = <3>; slew-rate = <3>;
}; };
pins3 {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
}; };
quadspi_sleep_pins_mx: quadspi_sleep_mx-0 { quadspi_sleep_pins_mx: quadspi_sleep_mx-0 {
...@@ -300,18 +294,6 @@ ...@@ -300,18 +294,6 @@
}; };
}; };
rtc_pins_mx: rtc_mx-0 {
pins {
pinmux = <STM32_PINMUX('C', 13, ANALOG)>; /* RTC_LSCO */
};
};
rtc_sleep_pins_mx: rtc_sleep_mx-0 {
pins {
pinmux = <STM32_PINMUX('C', 13, ANALOG)>; /* RTC_LSCO */
};
};
sdmmc1_pins_mx: sdmmc1_mx-0 { sdmmc1_pins_mx: sdmmc1_mx-0 {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
pins1 { pins1 {
...@@ -545,13 +527,17 @@ ...@@ -545,13 +527,17 @@
}; };
usb_otg_hs_pins_mx: usb_otg_hs_mx-0 { usb_otg_hs_pins_mx: usb_otg_hs_mx-0 {
u-boot,dm-pre-reloc;
pins { pins {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* USB_OTG_HS_ID */ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* USB_OTG_HS_ID */
}; };
}; };
usb_otg_hs_sleep_pins_mx: usb_otg_hs_sleep_mx-0 { usb_otg_hs_sleep_pins_mx: usb_otg_hs_sleep_mx-0 {
u-boot,dm-pre-reloc;
pins { pins {
u-boot,dm-pre-reloc;
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* USB_OTG_HS_ID */ pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* USB_OTG_HS_ID */
}; };
}; };
...@@ -568,13 +554,20 @@ ...@@ -568,13 +554,20 @@
}; };
&m4_rproc{ &m4_rproc{
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; /*Restriction: "memory-region" property is not managed - please to use User-Section if needed*/
mbox-names = "vq0", "vq1", "shutdown"; mboxes = <&ipcc 2>;
recovery; mbox-names = "shutdown";
status = "okay"; status = "okay";
/* USER CODE BEGIN m4_rproc */ /* USER CODE BEGIN m4_rproc */
/* USER CODE END m4_rproc */ /* USER CODE END m4_rproc */
m4_system_resources{
status = "okay";
/* USER CODE BEGIN m4_system_resources */
/* USER CODE END m4_system_resources */
};
}; };
&adc{ &adc{
...@@ -608,6 +601,31 @@ ...@@ -608,6 +601,31 @@
/* USER CODE END cryp1 */ /* USER CODE END cryp1 */
}; };
&dma1{
status = "okay";
/* USER CODE BEGIN dma1 */
/* USER CODE END dma1 */
};
&dma2{
status = "disabled";
/* USER CODE BEGIN dma2 */
/* USER CODE END dma2 */
};
&dmamux1{
dma-masters = <&dma1>;
dma-channels = <8>;
status = "okay";
/* USER CODE BEGIN dmamux1 */
/* USER CODE END dmamux1 */
};
&dts{ &dts{
status = "okay"; status = "okay";
...@@ -673,6 +691,13 @@ ...@@ -673,6 +691,13 @@
/* USER CODE END ipcc */ /* USER CODE END ipcc */
}; };
&iwdg2{
status = "okay";
/* USER CODE BEGIN iwdg2 */
/* USER CODE END iwdg2 */
};
&ltdc{ &ltdc{
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&ltdc_pins_mx>; pinctrl-0 = <&ltdc_pins_mx>;
...@@ -693,6 +718,48 @@ ...@@ -693,6 +718,48 @@
/* USER CODE END m_can1 */ /* USER CODE END m_can1 */
}; };
&m4_crc2{
status = "okay";
/* USER CODE BEGIN m4_crc2 */
/* USER CODE END m4_crc2 */
};
&m4_cryp2{
status = "okay";
/* USER CODE BEGIN m4_cryp2 */
/* USER CODE END m4_cryp2 */
};
&m4_dma2{
status = "okay";
/* USER CODE BEGIN m4_dma2 */
/* USER CODE END m4_dma2 */
};
&m4_hash2{
status = "okay";
/* USER CODE BEGIN m4_hash2 */
/* USER CODE END m4_hash2 */
};
&m4_rng2{
status = "okay";
/* USER CODE BEGIN m4_rng2 */
/* USER CODE END m4_rng2 */
};
&mdma1{
status = "okay";
/* USER CODE BEGIN mdma1 */
/* USER CODE END mdma1 */
};
&qspi{ &qspi{
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
...@@ -720,9 +787,6 @@ ...@@ -720,9 +787,6 @@
}; };
&rtc{ &rtc{
pinctrl-names = "default", "sleep";
pinctrl-0 = <&rtc_pins_mx>;
pinctrl-1 = <&rtc_sleep_pins_mx>;
status = "okay"; status = "okay";
/* USER CODE BEGIN rtc */ /* USER CODE BEGIN rtc */
...@@ -753,6 +817,13 @@ ...@@ -753,6 +817,13 @@
/* USER CODE END sdmmc2 */ /* USER CODE END sdmmc2 */
}; };
&tamp{
status = "okay";
/* USER CODE BEGIN tamp */
/* USER CODE END tamp */
};
&timers1{ &timers1{
status = "okay"; status = "okay";
......
conf/machine/cubemx/t1000-k/DeviceTree/t1000-k/tf-a/stm32mp15-mx.h → conf/machine/cubemx/t1000-k/CA7/DeviceTree/t1000-k/tf-a/stm32mp15-mx.dtsi
+ 25
− 25
View file @ c27c5e65
/* /*
* Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
* *
*/ */
/* /*
* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
* DDR type: DDR3 / DDR3L * DDR type: DDR3 / DDR3L
* DDR width: 16bits * DDR width: 16bits
* DDR density: 4Gb * DDR density: 4Gb
* System frequency: 528000Khz * System frequency: 528000kHz
* Relaxed Timing Mode: false * Relaxed Timing Mode: false
* Address mapping type: RBC * Address mapping type: RBC
* *
* Save Date: 2019.11.25, save Time: 18:28:16 * Save Date: 2021.11.30, save Time: 15:41:14
*/ */
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 528000Khz" #define DDR_MEM_NAME "DDR3-DDR3L 16bits 528000kHz"
#define DDR_MEM_SPEED 528000 #define DDR_MEM_SPEED 528000
#define DDR_MEM_SIZE 0x20000000 #define DDR_MEM_SIZE 0x20000000
#define DDR_MSTR 0x00041401 #define DDR_MSTR 0x00041401
#define DDR_MRCTRL0 0x00000010 #define DDR_MRCTRL0 0x00000010
...@@ -90,7 +90,7 @@ ...@@ -90,7 +90,7 @@
#define DDR_PTR2 0x042D9C80 #define DDR_PTR2 0x042D9C80
#define DDR_ACIOCR 0x10400812 #define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40 #define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200001F #define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B #define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x36D477D0 #define DDR_DTPR0 0x36D477D0
#define DDR_DTPR1 0x098A00D8 #define DDR_DTPR1 0x098A00D8
...@@ -109,11 +109,11 @@ ...@@ -109,11 +109,11 @@
#define DDR_DX1DLLCR 0x40000000 #define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0x00050500 #define DDR_DX1DQTR 0x00050500
#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000C881 #define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000 #define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF #define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000C881 #define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000 #define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF #define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000 #define DDR_DX3DQSTR 0x3DB02000
conf/machine/cubemx/t1000-k/CA7/DeviceTree/t1000-k/tf-a/stm32mp157c-t1000-k-mx-fw-config.dts 0 → 100644
+ 11
− 0
View file @ c27c5e65
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics.
*/
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
#include "stm32mp15-ddr-512m-fw-config.dts"
conf/machine/cubemx/t1000-k/DeviceTree/t1000-k/tf-a/stm32mp157c-t1000-k-mx.dts → conf/machine/cubemx/t1000-k/CA7/DeviceTree/t1000-k/tf-a/stm32mp157c-t1000-k-mx.dts
+ 63
− 31
View file @ c27c5e65
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/* /*
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics. * Author: STM32CubeMX code generation for STMicroelectronics.
*/ */
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
/dts-v1/; /dts-v1/;
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <dt-bindings/clock/stm32mp1-clksrc.h> #include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-mx.h" #include <dt-bindings/soc/st,stm32-etzpc.h>
#include "stm32mp15-mx.dtsi"
#include "stm32mp157c.dtsi" #include "stm32mp157.dtsi"
#include "stm32mp157cad-pinctrl.dtsi" #include "stm32mp15xc.dtsi"
#include "stm32mp15xxad-pinctrl.dtsi"
#include "stm32mp15-ddr.dtsi" #include "stm32mp15-ddr.dtsi"
#include "stm32mp157c-security.dtsi"
/* USER CODE BEGIN includes */ /* USER CODE BEGIN includes */
/* USER CODE END includes */ /* USER CODE END includes */
/ { / {
model = "STMicroelectronics custom STM32CubeMX board"; model = "STMicroelectronics custom STM32CubeMX board - openstlinux-5.10-dunfell-mp1-21-03-31";
compatible = "st,stm32mp157c-t1000-k-mx", "st,stm32mp157"; compatible = "st,stm32mp157c-t1000-k-mx", "st,stm32mp157";
/* USER CODE BEGIN root */ /* USER CODE BEGIN root */
...@@ -28,14 +34,16 @@ ...@@ -28,14 +34,16 @@
/* USER CODE END clocks */ /* USER CODE END clocks */
clk_lse: clk-lse { clk_lse: clk-lse {
/* USER CODE BEGIN clocks */ st,drive = < LSEDRV_MEDIUM_HIGH >;
/* USER CODE END clocks */
st,drive=<LSEDRV_MEDIUM_HIGH>; /* USER CODE BEGIN clk_lse */
/* USER CODE END clk_lse */
}; };
clk_hse: clk-hse { clk_hse: clk-hse {
/* USER CODE BEGIN clocks */
/* USER CODE END clocks */ /* USER CODE BEGIN clk_hse */
/* USER CODE END clk_hse */
}; };
}; };
...@@ -58,23 +66,12 @@ ...@@ -58,23 +66,12 @@
<STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */ <STM32_PINMUX('F', 6, AF9)>, /* QUADSPI_BK1_IO3 */
<STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */ <STM32_PINMUX('F', 7, AF9)>, /* QUADSPI_BK1_IO2 */
<STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */ <STM32_PINMUX('F', 8, AF10)>, /* QUADSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>; /* QUADSPI_BK1_IO1 */ <STM32_PINMUX('F', 9, AF10)>, /* QUADSPI_BK1_IO1 */
<STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
bias-disable; bias-disable;
drive-push-pull; drive-push-pull;
slew-rate = <3>; slew-rate = <3>;
}; };
pins3 {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QUADSPI_CLK */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
rtc_pins_mx: rtc_mx-0 {
pins {
pinmux = <STM32_PINMUX('C', 13, ANALOG)>; /* RTC_LSCO */
};
}; };
sdmmc1_pins_mx: sdmmc1_mx-0 { sdmmc1_pins_mx: sdmmc1_mx-0 {
...@@ -201,21 +198,30 @@ ...@@ -201,21 +198,30 @@
CLK_SAI3_DISABLED CLK_SAI3_DISABLED
CLK_SAI4_DISABLED CLK_SAI4_DISABLED
CLK_RNG1_CSI CLK_RNG1_CSI
CLK_RNG2_CSI
CLK_LPTIM1_DISABLED CLK_LPTIM1_DISABLED
CLK_LPTIM23_DISABLED CLK_LPTIM23_DISABLED
CLK_LPTIM45_DISABLED CLK_LPTIM45_DISABLED
>; >;
pll1:st,pll@0 { pll1:st,pll@0 {
cfg = < 2 80 0 1 1 1>; compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = < 2 80 0 1 1 PQR(1,0,0) >;
}; };
pll2:st,pll@1 { pll2:st,pll@1 {
cfg = < 2 65 1 1 0 7>; compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 1 0 PQR(1,1,1) >;
}; };
pll3:st,pll@2 { pll3:st,pll@2 {
cfg = < 2 97 3 1 1 1>; compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 49 2 2 1 PQR(1,0,0) >;
}; };
pll4:st,pll@3 { pll4:st,pll@3 {
cfg = < 5 124 9 9 9 3>; compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 5 124 9 9 9 PQR(1,1,0) >;
}; };
}; };
...@@ -232,6 +238,8 @@ ...@@ -232,6 +238,8 @@
/*"Non Secured" peripherals*/ /*"Non Secured" peripherals*/
DECPROT(STM32MP1_ETZPC_ADC_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_ADC_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_TT_FDCAN_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_TT_FDCAN_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
...@@ -247,9 +255,19 @@ ...@@ -247,9 +255,19 @@
DECPROT(STM32MP1_ETZPC_USART3_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_USART3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK) DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
/*"NS_R S_W" peripherals*/
DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
/*"Secured" peripherals*/
DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
/*"Mcu Isolation" peripherals*/
DECPROT(STM32MP1_ETZPC_CRC2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_CRYP2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_HASH2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
DECPROT(STM32MP1_ETZPC_RNG2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
/*Restriction: following IDs are not managed - please to use User-Section if needed: /*Restriction: following IDs are not managed - please to use User-Section if needed:
STM32MP1_ETZPC_DMA1_ID, STM32MP1_ETZPC_DMA2_ID, STM32MP1_ETZPC_DMAMUX_ID,
STM32MP1_ETZPC_SRAMx_ID, STM32MP1_ETZPC_RETRAM_ID, STM32MP1_ETZPC_BKPSRAM_ID*/ STM32MP1_ETZPC_SRAMx_ID, STM32MP1_ETZPC_RETRAM_ID, STM32MP1_ETZPC_BKPSRAM_ID*/
/* USER CODE BEGIN etzpc_decprot */ /* USER CODE BEGIN etzpc_decprot */
...@@ -265,6 +283,14 @@ ...@@ -265,6 +283,14 @@
/* USER CODE END etzpc */ /* USER CODE END etzpc */
}; };
&iwdg2{
status = "okay";
secure-status = "okay";
/* USER CODE BEGIN iwdg2 */
/* USER CODE END iwdg2 */
};
&qspi{ &qspi{
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&quadspi_pins_mx>; pinctrl-0 = <&quadspi_pins_mx>;
...@@ -291,8 +317,6 @@ ...@@ -291,8 +317,6 @@
}; };
&rtc{ &rtc{
pinctrl-names = "default";
pinctrl-0 = <&rtc_pins_mx>;
status = "okay"; status = "okay";
secure-status = "okay"; secure-status = "okay";
...@@ -318,6 +342,14 @@ ...@@ -318,6 +342,14 @@
/* USER CODE END sdmmc2 */ /* USER CODE END sdmmc2 */
}; };
&tamp{
status = "okay";
secure-status = "okay";
/* USER CODE BEGIN tamp */
/* USER CODE END tamp */
};
&uart4{ &uart4{
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_mx>; pinctrl-0 = <&uart4_pins_mx>;
......
conf/machine/cubemx/t1000-k/DeviceTree/t1000-k/u-boot/stm32mp15-mx.h → conf/machine/cubemx/t1000-k/CA7/DeviceTree/t1000-k/u-boot/stm32mp15-mx.dtsi
+ 25
− 25
View file @ c27c5e65
/* /*
* Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved * Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
* *
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
* *
*/ */
/* /*
* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs * File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
* DDR type: DDR3 / DDR3L * DDR type: DDR3 / DDR3L
* DDR width: 16bits * DDR width: 16bits
* DDR density: 4Gb * DDR density: 4Gb
* System frequency: 528000Khz * System frequency: 528000kHz
* Relaxed Timing Mode: false * Relaxed Timing Mode: false
* Address mapping type: RBC * Address mapping type: RBC
* *
* Save Date: 2019.11.25, save Time: 18:28:16 * Save Date: 2021.11.30, save Time: 15:41:14
*/ */
#define DDR_MEM_NAME "DDR3-DDR3L 16bits 528000Khz" #define DDR_MEM_NAME "DDR3-DDR3L 16bits 528000kHz"
#define DDR_MEM_SPEED 528000 #define DDR_MEM_SPEED 528000
#define DDR_MEM_SIZE 0x20000000 #define DDR_MEM_SIZE 0x20000000
#define DDR_MSTR 0x00041401 #define DDR_MSTR 0x00041401
#define DDR_MRCTRL0 0x00000010 #define DDR_MRCTRL0 0x00000010
...@@ -90,7 +90,7 @@ ...@@ -90,7 +90,7 @@
#define DDR_PTR2 0x042D9C80 #define DDR_PTR2 0x042D9C80
#define DDR_ACIOCR 0x10400812 #define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40 #define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200001F #define DDR_DSGCR 0xF200011F
#define DDR_DCR 0x0000000B #define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x36D477D0 #define DDR_DTPR0 0x36D477D0
#define DDR_DTPR1 0x098A00D8 #define DDR_DTPR1 0x098A00D8
...@@ -109,11 +109,11 @@ ...@@ -109,11 +109,11 @@
#define DDR_DX1DLLCR 0x40000000 #define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0x00050500 #define DDR_DX1DQTR 0x00050500
#define DDR_DX1DQSTR 0x3DB02000 #define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000C881 #define DDR_DX2GCR 0x0000CE80
#define DDR_DX2DLLCR 0x40000000 #define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF #define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000 #define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000C881 #define DDR_DX3GCR 0x0000CE80
#define DDR_DX3DLLCR 0x40000000 #define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF #define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000 #define DDR_DX3DQSTR 0x3DB02000
conf/machine/cubemx/t1000-k/DeviceTree/t1000-k/u-boot/stm32mp157c-t1000-k-mx-u-boot.dtsi → conf/machine/cubemx/t1000-k/CA7/DeviceTree/t1000-k/u-boot/stm32mp157c-t1000-k-mx-u-boot.dtsi
+ 45
− 30
View file @ c27c5e65
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause*/ /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause*/
/* /*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved * Copyright (C) 2021, STMicroelectronics - All Rights Reserved
* Author: STM32CubeMX code generation for STMicroelectronics. * Author: STM32CubeMX code generation for STMicroelectronics.
*/ */
/* For more information on Device Tree configuration, please refer to
* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h> #include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp15-mx.h" #include "stm32mp15-mx.dtsi"
#include "stm32mp157-u-boot.dtsi" #include "stm32mp15-u-boot.dtsi"
#include "stm32mp15-ddr.dtsi" #include "stm32mp15-ddr.dtsi"
/* USER CODE BEGIN includes */ /* USER CODE BEGIN includes */
...@@ -22,34 +26,41 @@ ...@@ -22,34 +26,41 @@
/* USER CODE BEGIN clocks */ /* USER CODE BEGIN clocks */
/* USER CODE END clocks */ /* USER CODE END clocks */
clk_hsi: clk-hsi { #ifndef CONFIG_TFABOOT
/* USER CODE BEGIN clocks */ clk_lsi: clk-lsi {
/* USER CODE END clocks */ status = "disabled";
u-boot,dm-pre-reloc;
/* USER CODE BEGIN clk_lsi */
/* USER CODE END clk_lsi */
}; };
clk_hsi: clk-hsi {
clk_csi: clk-csi { /* USER CODE BEGIN clk_hsi */
/* USER CODE BEGIN clocks */ /* USER CODE END clk_hsi */
/* USER CODE END clocks */
u-boot,dm-pre-reloc;
}; };
clk_csi: clk-csi {
clk_lse: clk-lse { /* USER CODE BEGIN clk_csi */
/* USER CODE BEGIN clocks */ /* USER CODE END clk_csi */
/* USER CODE END clocks */
st,drive=<LSEDRV_MEDIUM_HIGH>;
u-boot,dm-pre-reloc;
}; };
clk_lse: clk-lse {
st,drive = < LSEDRV_MEDIUM_HIGH >;
/* USER CODE BEGIN clk_lse */
/* USER CODE END clk_lse */
};
clk_hse: clk-hse { clk_hse: clk-hse {
/* USER CODE BEGIN clocks */
/* USER CODE END clocks */ /* USER CODE BEGIN clk_hse */
u-boot,dm-pre-reloc; /* USER CODE END clk_hse */
}; };
#endif /*CONFIG_TFABOOT*/
}; };
}; /*root*/ }; /*root*/
#ifndef CONFIG_TFABOOT
&rcc { &rcc {
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
st,clksrc = < st,clksrc = <
...@@ -106,24 +117,33 @@ ...@@ -106,24 +117,33 @@
CLK_SAI3_DISABLED CLK_SAI3_DISABLED
CLK_SAI4_DISABLED CLK_SAI4_DISABLED
CLK_RNG1_CSI CLK_RNG1_CSI
CLK_RNG2_CSI
CLK_LPTIM1_DISABLED CLK_LPTIM1_DISABLED
CLK_LPTIM23_DISABLED CLK_LPTIM23_DISABLED
CLK_LPTIM45_DISABLED CLK_LPTIM45_DISABLED
>; >;
pll1:st,pll@0 { pll1:st,pll@0 {
cfg = < 2 80 0 1 1 1>; compatible = "st,stm32mp1-pll";
reg = <0>;
cfg = < 2 80 0 1 1 PQR(1,0,0) >;
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
pll2:st,pll@1 { pll2:st,pll@1 {
cfg = < 2 65 1 1 0 7>; compatible = "st,stm32mp1-pll";
reg = <1>;
cfg = < 2 65 1 1 0 PQR(1,1,1) >;
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
pll3:st,pll@2 { pll3:st,pll@2 {
cfg = < 2 97 3 1 1 1>; compatible = "st,stm32mp1-pll";
reg = <2>;
cfg = < 1 49 2 2 1 PQR(1,0,0) >;
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
pll4:st,pll@3 { pll4:st,pll@3 {
cfg = < 5 124 9 9 9 3>; compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 5 124 9 9 9 PQR(1,1,0) >;
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
}; };
}; };
...@@ -135,13 +155,6 @@ ...@@ -135,13 +155,6 @@
/* USER CODE END qspi */ /* USER CODE END qspi */
}; };
&rcc{
u-boot,dm-pre-reloc;
/* USER CODE BEGIN rcc */
/* USER CODE END rcc */
};
&sdmmc1{ &sdmmc1{
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
...@@ -156,6 +169,8 @@ ...@@ -156,6 +169,8 @@
/* USER CODE END sdmmc2 */ /* USER CODE END sdmmc2 */
}; };
#endif /*CONFIG_TFABOOT*/
&uart4{ &uart4{
u-boot,dm-pre-reloc; u-boot,dm-pre-reloc;
......
conf/machine/cubemx/t1000-k/CA7/manifest.prop 0 → 100644
+ 4
− 0
View file @ c27c5e65
MANIFEST_VERSION = openstlinux-5.10-dunfell-mp1-21-03-31
KERNEL_DT = ./DeviceTree/t1000-k/kernel
UBOOT_DT = ./DeviceTree/t1000-k/u-boot
TFA_DT = ./DeviceTree/t1000-k/tf-a
conf/machine/cubemx/t1000-k/t1000-k.ioc
+ 182
− 132
View file @ c27c5e65
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