- Mar 26, 2016
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Add the basic support for Warp7 board. For more information about this reference design, please visit: https://www.element14.com/community/docs/DOC-79058/l/warp-7-the-next-generation-wearable-reference-platform Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com>
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CONFIG_BOARD_EARLY_INIT_F and CONFIG_BOARD_LATE_INIT should not be placed into mx7_common because not all boards need these options. Move them to the board file instead. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com>
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- Mar 25, 2016
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VESA 1024x768 results in much more accurate timings. Based on the patch from Soeren Moch for the tbs2910 board. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com>
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Make the watchdog registers 16-bit wide, as they are according to TRM. Signed-off-by:
Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com>
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Booting mx6qp sabreauto board and then doing: => saveenv => reset , causes a system hang. This happens because the size of the U-Boot binary is larger than CONFIG_ENV_OFFSET. Fix this problem by increasing CONFIG_ENV_OFFSET, so that the U-boot binary and the environment variables region do not overlap. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com>
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Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit() to generic implementation of wait_for_bit(). Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by:
Stefano Babic <sbabic@denx.de>
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Enable NAND TrimFFS support in M53EVK, since it is convenient when installing UBI images to NAND. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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Default print ARM clock for clocks command. Test on i.MX6UL 14x14 evk board: " => clocks PLL_SYS 792 MHz PLL_BUS 528 MHz PLL_OTG 480 MHz PLL_NET 50 MHz ARM 396000 kHz " Signed-off-by:
Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
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Configure the PMIC_STBY_REQ pin as open drain 100K according to the design team's requirement for the PMIC_STBY_REQ pin for i.MX 6UltraLite TO1.0. Signed-off-by:
Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
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To i.MX6UL, default ARM rate and AHB rate is 396M and 198M, no need to set them. Signed-off-by:
Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
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Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by:
Ye Li <ye.li@nxp.com> Signed-off-by:
Peng Fan <van.freenix@gmail.com> Acked-by:
Stefano Babic <sbabic@denx.de>
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- Mar 20, 2016
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Stefano Babic authored
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- Mar 18, 2016
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Simon Glass authored
Add some tests to check that block devices work as expected. Signed-off-by:
Simon Glass <sjg@chromium.org> Tested-by:
Stephen Warren <swarren@nvidia.com>
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Simon Glass authored
Driver model is used for host device block devices now, so we don't need the old code. Remove it. Signed-off-by:
Simon Glass <sjg@chromium.org> Tested-by:
Stephen Warren <swarren@nvidia.com>
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Simon Glass authored
Now that the drivers used by sandbox support CONFIG_BLK, we can switch sandbox over to use driver model for block devices. Signed-off-by:
Simon Glass <sjg@chromium.org> Tested-by:
Stephen Warren <swarren@nvidia.com>
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Simon Glass authored
When 'usb start' is used, block devices are created for any USB flash sticks and disks, etc. When 'usb stop' is used, these block devices are currently not removed. We don't want old block devices hanging around since they can still be visible to U-Boot. Therefore, when USB is shut down, remove and unbind all the block devices created by the USB subsystem. Possibly we should unbind all devices which don't cause problems by being unbound. Most likely we can remove everything except USB controllers, hubs and emulators. We can consider that later. Signed-off-by:
Simon Glass <sjg@chromium.org> Tested-by:
Stephen Warren <swarren@nvidia.com>
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Simon Glass authored
This option outputs to the log file, not to the terminal. Clarify that in the help, and add a mention of it in the README. Signed-off-by:
Simon Glass <sjg@chromium.org> Reported-by:
Stephen Warren <swarren@wwwdotorg.org> Reviewed-by:
Stephen Warren <swarren@nvidia.com>
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Simon Glass authored
At present buildman allows you to specify the directory containing the toolchain, but not the actual toolchain prefix. If there are multiple toolchains in a single directory, this can be inconvenient. Add a new 'toolchain-prefix' setting to the settings file, which allows the full prefix (or path to the C compiler) to be specified. Update the documentation to match. Suggested-by:
Stephen Warren <swarren@wwwdotorg.org> Reviewed-by:
Joe Hershberger <joe.hershberger@ni.com> Signed-off-by:
Simon Glass <sjg@chromium.org> Tested-by:
Stephen Warren <swarren@nvidia.com>
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Simon Glass authored
At present if you try to use buildman with the branch 'test' it will complain that it is unsure whether you mean the branch or the directory. This is a feature of the 'git log' command that buildman uses. Fix it by resolving the ambiguity. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Joe Hershberger <joe.hershberger@ni.com>
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Michal Simek authored
reg-offset is the part of standard 8250 binding in the kernel. It is shifting start of address space by reg-offset. On Xilinx platform this offset is typically 0x1000. Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com> Moved the new field to the end of the struct to avoid problems: Signed-off-by:
Simon Glass <sjg@chromium.org>
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Przemyslaw Marczak authored
This reverts commit 71105f50. The reverted commit was applied for a temporary to unbreak few Exynos boards on the release. After the discussion about the change, this commit should be avoided. Fixed device-tree for Exynos, allows reverting it without any issues. Signed-off-by:
Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by:
Simon Glass <sjg@chromium.org> Acked-by:
Simon Glass <sjg@chromium.org>
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Przemyslaw Marczak authored
This change is required to avoid warnings about invalid size-cells defined in device-tree pinctrl nodes for Exynos. Tested on: - Odroid U3 - Odroid XU3 Signed-off-by:
Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by:
Simon Glass <sjg@chromium.org> Acked-by:
Simon Glass <sjg@chromium.org> Acked-by:
Minkyu Kang <mk7.kang@samsung.com>
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Simon Glass authored
Some controllers do not allow the output value to be read. Detect this and report the error in that case. Signed-off-by:
Simon Glass <sjg@chromium.org>
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- Mar 17, 2016
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Tom Rini authored
Since dhry_per_sec is a u64 we must also use lldiv here when working with it. Otherwise: ../lib/dhry/cmd_dhry.c:(.text.do_dhry+0xd8): undefined reference to `__udivdi3' On some platforms. Signed-off-by:
Tom Rini <trini@konsulko.com>
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Stefan Roese authored
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, installed on the congatec Qseven 2.0 evaluation carrier board (conga-QEVAL). Its port is very similar to the MinnowboardMAX port and also uses the Intel FSP as described in doc/README.x86. Currently supported are the following interfaces / devices: - UART (via Winbond legacy SuperIO chip on carrier board) - Ethernet (PCIe Intel I210 / E1000) - SPI including SPI NOR as boot-device - USB 2.0 - SATA via U-Boot SCSI IF - eMMC - Video (HDMI output @ 800x600) - PCIe Not supported yet is: - I2C - USB 3.0 Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI without any 16-bit init. This can help during development by allowing U-Boot to avoid doing all the init required by the platform. U-Boot expects its GDT to be set up correctly by its 16-bit code. If coreboot doesn't do this (because it hasn't run the payload setup code yet) then this won't happen. In this case we cannot rely on the GDT settings. U-Boot will hang or crash if these are wrong. Provide a development-only option to set up the GDT correctly. This is just a hack so you can jump to U-Boot from any stage of coreboot, not just at the end. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
This is not needed now that the memory controller driver has the SPD data in its own node. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
At present samus reports about 5600 DMIPS. With the default iteration count this is OK, but if 10 million runs are performed it overflows. Fix it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
This is missing, with causes lldiv() to fail on boards with use the private libgcc. Add the missing routine. Code is available for using the CLZ instruction but it is not enabled at present. This comes from coreboot version 4.0. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
There is an extra line in the comment in the header. Remove it. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
Add a function to set the ID in the IOAPIC. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
Update a few points which have become out-of-date. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
This is a little easier on the eyes, particularly when the backlight is set to maximum. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
Add an address which can be used for loading and running the reference code when needed. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
Add a video driver for Intel's broadwell integrated graphics controller. This uses a binary blob for most init, with the driver just performing a few basic tasks. This driver supports VESA as the mode-setting mechanism. Since most boards don't support driver model yet with VESA, a special case is added to the Kconfig for broadwell. Eventually all boards will use driver model and this can be removed. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
Provide a way to determine the HSIO (high-speed I/O) version supported by the Intel Management Engine (ME) implementation on the platform. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Bin Meng <bmeng.cn@gmail.com>
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