- May 13, 2015
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Simon Glass authored
Connect up the clocks and the eDP driver to make these displays work with Tegra124-based devices. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
This interface is used on laptop devices based on Tegra. Add a driver which provides access to the eDP interface. The driver uses the display port uclass. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
The SOR is required for talking to eDP LCD panels. Add a driver for this which will be used by the DisplayPort driver. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Add the various host1x peripherals to allow an eDP display to be connected. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
eDP (Embedded DisplayPort) is a standard widely used in laptops to drive LCD panels. Add a uclass for this which supports a few simple operations. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
For digital displays (such as EDP LCDs) we would like to read the EDID information and use that to set display timings. Provide a function to do this. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
This file (from Linux 3.17) provides defines for display port. Use it so that our naming is consistent with Linux. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Allow this to be used by other Tegra SoCs. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Add functions to provide access to the display clocks on Tegra124 including setting the clock rate for an EDP display. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Create a function which sets the source clock for a peripheral, given the number of mux bits to adjust. This can then be used more generally. For now, don't export it. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
The get_pll() function can do the wrong thing if passed values that are out of range. Add checks for this and add a function which can return a 'simple' PLL. This can be defined by SoCs with their own clocks. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Instead of CONFIG_VIDEO_TEGRA, use CONFIG_LCD to determine whether an LCD is present. Tegra124 uses a different driver. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
This peripheral is required to get the LCD display running. Add it to tegra124 and also bring in the binding file from Linux 3.18 Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Add required setup for the LCD display, and a function to provide the board ID. This requires GPIOs to be available prior to relocation. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Add support for this PMIC which is used on some Tegra124 boards. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Some LCDs require a PMIC to be set up - add a function for this. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
With the full PMIC framework we may be able to avoid this. But for now we need access to the PMIC. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Add a way of displaying a numeric board ID on start-up. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
This is only used by Nvidia boards, so move it into nvidia/common to simplify things. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
When enabling a PWM, allow the existing clock rate and source to stand unchanged. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
This is needed for tegra124 also, so make it common and add a header file for tegra124. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
This is useful for display parameters. Add a simple decode function to read from this device tree node. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
gpio_get_values_as_int() should return an error if something goes wrong. Also provide gpio_claim_vector(), a function to request the GPIOs and set them to input mode. Otherwise callers have to do this themselves. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Simon Glass authored
Sort uclasses into alphabetical order and tidy up the comments. Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- May 12, 2015
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Joe Hershberger authored
In order to reduce merge conflicts and to maintain the simplest possible defconfig files, we should be using the savedefconfig feature of Kconfig every time a new feature is added. This keeps the defconfig settings to a minimum (only those things not default) and keeps them in the same order as the Kconfig options. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
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Joe Hershberger authored
By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
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- May 10, 2015
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Tom Rini authored
As per the author, we don't need this patch really since the other patch "stm32f4: fix serial output" superseded it. This reverts commit 85e5f5b7. Signed-off-by:
Tom Rini <trini@konsulko.com>
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Joe Hershberger authored
Having this as a Kconfig allows it to be a dependent feature. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Stefan Roese authored
As this board seems to be unmaintained for quite some time, and its not moved to the generic board ingrastructure, lets remove it. This will also enable us to remove the CONFIG_AUTOBOOT_DELAY_STR2 and CONFIG_AUTOBOOT_STOP_STR2 macros, as this sc3 board is the only one using one of this macros. A removal patch will follow soon. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Juergen Beisert <jbeisert@eurodsn.de> Acked-by:
Heiko Schocher <hs@denx.de>
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Vikas Manocha authored
This patch adds device tree support for arm pl010/pl011 driver. Signed-off-by:
Vikas Manocha <vikas.manocha@st.com> Acked-by:
Simon Glass <sjg@chromium.org>
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Joe Hershberger authored
Introduced in change d20a40de "Roll crc32 into hash infrastructure" The crc32 command with no -v expects an optional 3rd argument to be an address to store the result in. With the -v switch, the last argument is a crc, not an address. In the case where -v is set, we should set the HASH_FLAG_ENV flag since that will first look for the value to be a digest value, which matches the expected API for the crc32 command. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Joe Hershberger authored
Introduced in change d20a40de "Roll crc32 into hash infrastructure" Use a consistent define to enable the verify feature in crc32 command. Signed-off-by:
Joe Hershberger <joe.hershberger@ni.com> Acked-by:
Simon Glass <sjg@chromium.org>
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Du Huanpeng authored
Signed-off-by:
Du Huanpeng <u74147@gmail.com>
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Vikas Manocha authored
This patch ignores the serial port static platform data at compilation time in case of device tree control. Signed-off-by:
Vikas Manocha <vikas.manocha@st.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Vikas Manocha authored
This patch adds device tree for the ST Micro stv0991 board & enables device tree control. Progressively device tree support for the drivers being used will also be added. Signed-off-by:
Vikas Manocha <vikas.manocha@st.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Arun Bharadwaj authored
U-Boot has been broken on Overo boards since commit a6b541b0. This is because the gd pointer is not set early enough anymore, such that the i2c_set_bus_num in get_board_revision can safely execute. This results in a console hang at SPL and the boot does not proceed. This piece of code is anyway necessary only for really old Overo boards with revision numbers <= 2410 and not required for the newer boards. For these older boards, u-boot v2014.10 still works fine. Signed-off-by:
Arun Bharadwaj <arun@gumstix.com>
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Arun Bharadwaj authored
This separates the SPL-specific code from the u-boot-specific code for the Overo board following the discussion at http://lists.denx.de/pipermail/u-boot/2015-April/211622.html The code is split up into spl.c, overo.c and common.c (which has the code common to both) Signed-off-by:
Arun Bharadwaj <arun@gumstix.com>
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Ash Charles authored
If regular NAND booting fails to find a valid uImage in the kernel partition in NAND, try to boot using a zImage and dtb found in a UBI volume in the rootfs partition. This is the NAND analog of mmc zImage booting for device-tree based kernels. Signed-off-by:
Ash Charles <ashcharles@gmail.com> Signed-off-by:
Arun Bharadwaj <arun@gumstix.com>
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Ash Charles authored
Overo COMs have NAND flash that requires 4-bit ECC or better except for the first sector which can use 1-bit ECC. The boot ROM expects to load a payload from NAND written using 1-bit hardware-based ECC. In short, write SPL to NAND something like this (4 times for redundancy): #> nandecc hw #> nand write ${loadaddr} 0x0 ${filesize} #> nand write ${loadaddr} 0x20000 ${filesize} #> nand write ${loadaddr} 0x40000 ${filesize} #> nand write ${loadaddr} 0x60000 ${filesize} Then, switch back to software-based BCH8 for everything else: #> nandecc sw bch8 After [1], enlarge the max size of the SPL so the BCH code can fit. [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg163912.html Signed-off-by:
Ash Charles <ashcharles@gmail.com>
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Ash Charles authored
Signed-off-by:
Ash Charles <ashcharles@gmail.com>
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