- Oct 21, 2008
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Stefan Roese authored
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- Oct 18, 2008
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Wolfgang Denk authored
Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Jason Jin authored
Signed-off-by:
Jason Jin <Jason.jin@freescale.com>
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Liu Yu authored
This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by:
Liu Yu <yu.liu@freescale.com>
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Liu Yu authored
The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by:
Liu Yu <yu.liu@freescale.com>
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Ed Swarthout authored
Signed-off-by:
Ed Swarthout <Ed.Swarthout@freescale.com>
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Ed Swarthout authored
Debug sessions may have left enabled laws. Changing lawbar with an unkown enabled tgtid could cause problems. Signed-off-by:
Ed Swarthout <Ed.Swarthout@freescale.com>
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Ed Swarthout authored
mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0. Include host_agent == 0 decode for end-point determination. This is not needed for the ds reference board since pcie3 will be a host in order to connect to the uli chip. Include it here as a reference for other mpc8572 boards. Signed-off-by:
Ed Swarthout <Ed.Swarthout@freescale.com>
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Ed Swarthout authored
Signed-off-by:
Ed Swarthout <Ed.Swarthout@freescale.com>
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Ed Swarthout authored
Signed-off-by:
Ed Swarthout <Ed.Swarthout@freescale.com>
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Andy Fleming authored
Some cores don't support ethernet stashing at all, and some instances have errata. Adds 3 properties to gianfar nodes which support stashing. For now, just add this support to 85xx SoCs. Signed-off-by:
Andy Fleming <afleming@freescale.com>
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Haiying Wang authored
* Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. Signed-off-by:
James Yang <James.Yang@freescale.com> Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Haiying Wang authored
* Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by:
James Yang <James.Yang@freescale.com> Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Haiying Wang authored
Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Haiying Wang authored
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and ba_intlv_ctl. * Print DDR interleaving mode information * Add doc/README.fsl-ddr to describe the interleaving setting Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Haiying Wang authored
Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Haiying Wang authored
Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Kumar Gala authored
Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Changing the flash from cacheable to cache-inhibited was taking a significant amount of time due to the fact that we were iterating over the full 256M of flash. Instead we can just flush the L1 d-cache and invalidate the i-cache. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Heiko Schocher authored
in ft_blob_update () for both boards was an unneccessary repetition of code, which this patch moves in a common function for this boards. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Kumar Gala authored
Each architecture has different ways of determine what regions of memory might not be valid to get overwritten when we boot. This provides a hook to allow them to reserve any regions they care about. Currently only ppc, m68k and sparc need/use this. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Kumar Gala authored
Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Sub-command can benefit from using the same table and search functions that top level commands have. Expose this functionality by refactoring find_cmd() and introducing find_cmd_tbl() that sub-command processing can call. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
The EEprom contains some Manufacturerinformation, which are read from u-boot at boot time, and saved in same hush shell variables. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
This new command shows the local variables defined in the hush shell: => help showvar showvar - print values of all hushshell variables showvar name ... - print value of hushshell variable 'name' Also make the set_local_var() and unset_local_var () no longer static, so it is possible to define local hush shell variables at boot time. If CONFIG_HUSH_INIT_VAR is defined, u-boot calls hush_init_var (), where boardspecific code can define local hush shell variables at boottime. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
With this Command it is possible to add new I2C Busses, which are behind 1 .. n I2C Muxes. Details see README. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
As documented in doc/I2C_Edge_Conditions, adding a board specific deblocking mechanism via CFG_I2C_INIT_BOARD for the mgcoge and mgsuvd board. This code was originally written by Keymile in association with Anatech and Atmel in 1998. The Code toggels the SCL until the SCA line goes to HIGH (max. 16 times). And after this, a start condition is sent. This is another approach to deblock the I2C Bus. The soft I2C driver actually sends 9 clocks with SDA High, and then a stop at the end, to deblock the I2C Bus. Maybe we should use the approach from Keymile as the new standard? Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
This patch adds the option for a boardspecific I2C deblocking mechanism for the soft i2c driver. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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