- Oct 18, 2008
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Jason Jin authored
Signed-off-by:
Jason Jin <Jason.jin@freescale.com>
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Liu Yu authored
This patch based on Andy's work. Including command 'pixis_set_sgmii' support. Signed-off-by:
Liu Yu <yu.liu@freescale.com>
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Liu Yu authored
The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by:
Liu Yu <yu.liu@freescale.com>
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Haiying Wang authored
* Add board specific parameter table to choose correct cpo, clk_adjust, write_data_delay, 2T based on board ddr frequency and n_ranks. * Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#. * Set memory controller interleaving mode to bank interleaving, and disable bank(chip select) interleaving mode by default, because the default on-board DDR DIMMs are 2x512MB single-rank. * Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000. Signed-off-by:
James Yang <James.Yang@freescale.com> Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Kumar Gala authored
Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
The EEprom contains some Manufacturerinformation, which are read from u-boot at boot time, and saved in same hush shell variables. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
With this Command it is possible to add new I2C Busses, which are behind 1 .. n I2C Muxes. Details see README. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
As documented in doc/I2C_Edge_Conditions, adding a board specific deblocking mechanism via CFG_I2C_INIT_BOARD for the mgcoge and mgsuvd board. This code was originally written by Keymile in association with Anatech and Atmel in 1998. The Code toggels the SCL until the SCA line goes to HIGH (max. 16 times). And after this, a start condition is sent. This is another approach to deblock the I2C Bus. The soft I2C driver actually sends 9 clocks with SDA High, and then a stop at the end, to deblock the I2C Bus. Maybe we should use the approach from Keymile as the new standard? Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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Haiying Wang authored
Change UEC phy interface from GMII to RGMII on MPC8568MDS board Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed, but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable. Now both UEC1 and UEC2 can work properly under u-boot. It is also in consistent with the kernel setting for 8568 UEC phy interface. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
Ben Warren <biggerbadderben@gmail.com>
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- Oct 17, 2008
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de> Signed-off-by:
Wolfgang Denk <wd@denx.de>
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Heiko Schocher authored
Signed-off-by:
Heiko Schocher <hs@denx.de>
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- Oct 14, 2008
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Selvamuthukumar authored
Currently this is not creating any problem. But it will result in compilation error when used as below. printf("CFG_SDRAM_CFG2 - %08x\n", CFG_SDRAM_CFG2); Signed-off-by:
Selvamuthukumar <selva.muthukumar@e-coninfotech.com> continuation of the theme based on git grep "^#define CFG_.*;$" include/ Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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Peter Tyser authored
Signed-off-by:
Peter Tyser <ptyser@xes-inc.com>
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Nobuhiro Iwamatsu authored
Signed-off-by:
Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by:
Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- Oct 10, 2008
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Matthias Fuchs authored
Signed-off-by:
Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by:
Stefan Roese <sr@denx.de>
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- Oct 08, 2008
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Kumar Gala authored
Commit 445a7b38 introduced the following compile warnings: cmd_i2c.c:112: warning: missing braces around initializer cmd_i2c.c:112: warning: (near initialization for 'i2c_no_probes[0]') Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Guennadi Liakhovetski authored
Switch to the standard CFG_HZ=1000 value, while at it, minor white-space cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads, provides 2% or 0.4% precision depending on the CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s boot-delay. Signed-off-by:
Guennadi Liakhovetski <lg@denx.de>
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- Oct 07, 2008
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Haiying Wang authored
Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Haiying Wang authored
The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for system information like mac addresses etc. This patch enables it. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Haiying Wang authored
MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1 according to the board spec, and adds the 2nd i2c bus offset. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com>
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Jason Jin authored
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by:
Jason Jin <Jason.jin@freescale.com>
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- Oct 01, 2008
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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- Sep 24, 2008
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Kim Phillips authored
bootdelay set to -1 'permanently' disables autobooting, even if bootcmd is specified. Change to a positive value to allow autobooting when a bootcmd is set. Reported-by:
Coray Tate <Coray.Tate@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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Kim Phillips authored
the operating system may leave flash in a h/w locked state after writing. This allows u-boot to continue to write flash by enabling h/w unlocking by default. Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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- Sep 22, 2008
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Anatolij Gustschin authored
Running mtest command on socrates without specifying an address range crashes the board. This patch changes default mtest address range to prevent this behavior. Signed-off-by:
Anatolij Gustschin <agust@denx.de>
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Anatolij Gustschin authored
Commit be0bd823 changed SPD EEPROM address to 0x51 and DDR SDRAM detection stopped working. Change this address back to 0x50. Signed-off-by:
Anatolij Gustschin <agust@denx.de>
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- Sep 18, 2008
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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- Sep 16, 2008
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Wolfgang Denk authored
After switching to using the CFI flash driver, the correct remapping of the flash banks was forgotten. Also, some boards were not adapted, and the old legacy flash driver was not removed yet. Signed-off-by:
Wolfgang Denk <wd@denx.de>
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- Sep 13, 2008
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u-boot@bugs.denx.de authored
Signed-off-by:
Detlev Zundel <dzu@denx.de>
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- Sep 12, 2008
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Stefan Roese authored
Signed-off-by:
Stefan Roese <sr@denx.de>
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