fdts: disable DDR3 read/write ordering for STM32MP15

Ordering between read and write transactions should be disabled on each
port.
The DDR controller ensures that all read/write commands from the
application port interface are transported to the DFI interface in the
order of appearance.

Change-Id: I70c16cfe6c8ae2587d1131c3e7ddf183d20a3bb7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184352


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Tested-by: Yann GAUTIER <yann.gautier@st.com>

fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi

@@ -61,13 +61,13 @@
 #define DDR_DBGCMD 0x00000000
 #define DDR_POISONCFG 0x00000000
 #define DDR_PCCFG 0x00000010
-#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGR_0 0x00000000
 #define DDR_PCFGW_0 0x00000000
 #define DDR_PCFGQOS0_0 0x02100C03
 #define DDR_PCFGQOS1_0 0x00800100
 #define DDR_PCFGWQOS0_0 0x01100C03
 #define DDR_PCFGWQOS1_0 0x01000200
-#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGR_1 0x00000000
 #define DDR_PCFGW_1 0x00000000
 #define DDR_PCFGQOS0_1 0x02100C03
 #define DDR_PCFGQOS1_1 0x00800040

fdts/stm32mp15-ddr3-2x4Gb-1066-binG.dtsi

@@ -61,13 +61,13 @@
 #define DDR_DBGCMD 0x00000000
 #define DDR_POISONCFG 0x00000000
 #define DDR_PCCFG 0x00000010
-#define DDR_PCFGR_0 0x00010000
+#define DDR_PCFGR_0 0x00000000
 #define DDR_PCFGW_0 0x00000000
 #define DDR_PCFGQOS0_0 0x02100C03
 #define DDR_PCFGQOS1_0 0x00800100
 #define DDR_PCFGWQOS0_0 0x01100C03
 #define DDR_PCFGWQOS1_0 0x01000200
-#define DDR_PCFGR_1 0x00010000
+#define DDR_PCFGR_1 0x00000000
 #define DDR_PCFGW_1 0x00000000
 #define DDR_PCFGQOS0_1 0x02100C03
 #define DDR_PCFGQOS1_1 0x00800040