Ordering between read and write transactions should be disabled on each
port.
The DDR controller ensures that all read/write commands from the
application port interface are transported to the DFI interface in the
order of appearance.

Change-Id: I70c16cfe6c8ae2587d1131c3e7ddf183d20a3bb7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184352


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Tested-by: Yann GAUTIER <yann.gautier@st.com>