Increase GPU clock

See merge request !4

Increase GPU clock for SOM from 264MHz to 528MHz to its limit

stm32mp-t1000: Fix clock configuration

See merge request !3

Fix some overclocking for SAI interfaces. Also some clock
configurations are improved. Changed clocks are:

- SAI1 to SAI4
- UART1
- UART78
- SDMMC3

Integrate changes of v2.4-stm32mp-r2.1 version from ST

See merge request !2

When SSP is built using USB mode, all UART nodes are
disabled except console. Aliases must be also removed.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I7d6778641444888ccb074f4d0634a509caedf65c
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/254886


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>

Remove the old regulator files that are no more
available.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ib122e6a5b906e4a4b2ab529c6bdb0f6996704b79
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/254885


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>

Gateable clocks, listed in stm32mp1_clk_gate[] table, get resumed in
stm32mp1_clock_resume() function, when returning from Standby state.
If a clock is always-on, like RTC, it doesn't get a refcount. So the
resume function tries to disable it. Such clocks should then be skipped
in the gate resume loop.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iac7e977fa4916614522a2270a44f08f243238943
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/230363


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/230856


Reviewed-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>
Tested-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>

ECDSA signatures can not guarantee the exact 32 bits that must
be given to the hardware. We must check the ASN1 sequence and
adapt the R,S tuple to manage a proper 2 * 32 bytes whatever
the certificate content.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I456c32aa1d081562c2787866894f3be3b6f8cb9d
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/252923


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>

On battery powered systems the RTC keeps the date/time across
system reboot.
The RTC clock should not be disabled otherwise the date/time
counter gets stopped.

Tag RTC clock as always on.

Signed-off-by: HE Shushan <shushan.he@st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I6455c3c740d2e5add28255eb84f8ebaf2870d9d8
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/225732


Tested-by: Yann GAUTIER <yann.gautier@foss.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>
Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Antonio Maria BORNEO <antonio.borneo@st.com>
Reviewed-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>

Also change cpu voltage when restoring mpu frequency.

Change-Id: Ifef230e836f7dc43ee56f117d467aa6b7eccb92a
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/236418


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>

Rename stm32mp1_set_opp_khz to stm32mp1_set_mpu_freq
as it does not handle cpu voltage.

Change-Id: I32ecc1c0c88d01e41982a45dffe68f9f657b7d2d
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/236417


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>

Fix some bad register usage and incorrect mask used
to manage the tamper events.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: If38436150b80c5d5be95e2d802d9541bd6f5b2e4
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/251180


Tested-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>
Reviewed-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>

Add support for regulator-always-on at BL2 level as it was supported
before using the regulator framework.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: Idb2f4ddc2fdd4e0d31fb33da87c84618aa2e5135
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/237827


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>
Tested-by: Yann GAUTIER <yann.gautier@foss.st.com>

To get the nearest divisor for BRR register, we use:
Divisor =  (Uart clock + (baudrate / 2)) / baudrate
But lsl was wrongly used instead of lsr to have the division by 2.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Iedcc3ccdb4cf8268012e82a66df2a9ec48fc1d79
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/241996


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I368aa126ca10d218038ce0f3d85ab4fe6f1a5e60

bsec: Add write lock and shadow register update

See merge request !1

Add automatic otp register lock for all registers after register 56. Also
add additional output which registers are permanent locked (on boot)
or if a register read failed (disturbed or inconsistent)

Add kontron and user reserved otp register access

Use device tree files from CubeIDE version 1.8.0
Add missing one.

Use device tree files from CubeIDE version 1.8.0

STM32MP release v2.4-stm32mp1-r2

DDR: DQS Tuning: Add RVTRN (for LPDDR2 / LPDDR3)
Enable ETH PTP clock tree by default on STM32MP15 boards
Manage backup registers security at BL32 level
Fix the shutdown via PMIC switch off
Improve boot time in FIP mode using mmc interfaces
Fix RTC clock rate
Display bootrom authentication trace
Fixes

Access to additional OTP values requires additional key in dts file

- activate crc, cryp, hash, rng for M4
- remove rtc pins
- update compatibility string

Add dummy configuration to enable compile for this machine

In fixup_gdt_reloc(), do not skip the last address (__RW_END__) for
dynamic relocations.
Else, the invalidation of the data done under _init_c_runtime in
el3_entrypoint_common macro will not be correct.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1166a59ac964ec8ad4e099cb3600e843afc71d82
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/225705


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@foss.st.com>
Reviewed-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>

Currently on image entry, the data cache in the RW address range is
invalidated before MMU is enabled to safeguard against potential
stale data from previous firmware stage. If PIE is enabled however,
RO sections including the GOT may be also modified during pie fixup.
Therefore, to be on the safe side, invalidate the entire image
region if PIE is enabled.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I7ee2a324fe4377b026e32f9ab842617ad4e09d89
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/225704


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>
Reviewed-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>
Tested-by: Yann GAUTIER <yann.gautier@foss.st.com>

Fix a Data abort while trying to invalidate data at address 0.
When the partition is skipped, the invalidate must not be done
as the bl_info are not filled.

Change-Id: Ib90f1a7ac55648a9228e6dc53b875265a4eede32
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/214784


Tested-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/224185


Tested-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>
Reviewed-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>

In BL32, only skip UART initialization if UART enable bit is set.
Due to patch [1], a reset of UART is done in crash console init.
In this case, UART should then be reconfigured.

[1] 7fa2e96e ("stm32mp1: add UART reset in crash console init")

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I650d4c387b60dd74b780e6f3adfd629ea44f5834
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/219107


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>

Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7ac1c77c21ebc30315b532741f2f255c2312d5b2
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/219163


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@foss.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>

When RTC clock source is HSE, the RTCDIV is not taken into account.

Change-Id: I1613b638e8932c03f3349adb01e13f5294a3bf5d
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/216524


Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>
Reviewed-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Tested-by: Yann GAUTIER <yann.gautier@foss.st.com>

If a PAD reset occurs during Standby, a cold boot should be done, and
not a return from Standby. The wakeup_standby variable should then be
false in this case.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I76d79bbf3702767209a8fa59980a86268f24c554
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/217698


Reviewed-by: CITOOLS <MDG-smet-aci-reviews@list.st.com>
Reviewed-by: CIBUILD <MDG-smet-aci-builds@list.st.com>
Reviewed-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>

Save last opp frequency before to enter in standby and restore it
at resume to avoid de-synchronization between TF-A (BL2/32) and
the kernel Linux.

Change-Id: Ib2bd54c05ac6e221e39498a4a15653fe39e3ada9
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/216791


Reviewed-by: Yann GAUTIER <yann.gautier@foss.st.com>
Reviewed-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>