fdt.c:91:78: warning: Using plain integer as NULL pointer
fdt.c:103:78: warning: Using plain integer as NULL pointer
speed.c:55:11: warning: symbol 'corecnf_tab' was not declared. Should it be static?
speed.c:519:5: warning: symbol 'do_clocks' was not declared. Should it be static?
mpc8313erdb.c:73:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:74:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:75:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:76:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:79:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:80:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:81:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:82:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:85:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:86:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:87:17: warning: obsolete struct initializer, use C99 syntax
mpc8313erdb.c:88:17: warning: obsolete struct initializer, use C99 syntax

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static?
cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static?
bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart'
bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write'
bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write'
bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio'
bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write'
bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write'
bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec'
bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect'
ngpixis.c:245:1: error: directive in argument list
ngpixis.c:247:1: error: directive in argument list

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

ctrl_regs.c:31:5: warning: symbol 'fsl_ddr_get_version' was not declared. Should it be static?
cpu.c:135:14: warning: non-ANSI function declaration of function 'cpu_mask'
cpu.c:154:18: warning: non-ANSI function declaration of function 'cpu_numcores'
cpu.c:37:17: warning: symbol 'cpu_type_list' was not declared. Should it be static?
cpu.c:117:17: warning: symbol 'cpu_type_unknown' was not declared. Should it be static?
fsl_lbc.c:14:6: warning: symbol '__lbc_sdram_init' was not declared. Should it be static?

and:

lc_common_dimm_params.c:15:1: warning: symbol 'compute_cas_latency_ddr3' was not declared. Should it be static?

making it static produces the following compiler warning:

lc_common_dimm_params.c:15:1: warning: 'compute_cas_latency_ddr3' defined but not used [-Wunused-function]

so we protect it with the preprocessor.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

traps.c:*:1: warning: symbol 'print_backtrace' was not declared. Should it be static?
traps.c:93:1: warning: symbol '_exception' was not declared. Should it be static?
board.c:166:6: warning: symbol '__board_add_ram_info' was not declared. Should it be static?
board.c:174:5: warning: symbol '__board_flash_wp_on' was not declared. Should it be static?
board.c:187:6: warning: symbol '__cpu_secondary_init_r' was not declared. Should it be static?
board.c:265:12: warning: symbol 'init_sequence' was not declared. Should it be static?
board.c:348:5: warning: symbol '__fixup_cpu' was not declared. Should it be static?
board.c:405:53: warning: Using plain integer as NULL pointer

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

extable.c:66:9: warning: symbol 'ex_tab_message' was not declared. Should it be static?

making it static can produce a new build warning on some boards:

extable.c:66:12: warning: 'ex_tab_message' defined but not used [-Wunused-variable]

but ex_tab_message doesn't do much even when used, so just remove it.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

a fixup __iomem definition in arch code appears to be placed there as a cover
up from a code import from linux when u-boot didn't yet have a compiler.h,
introduced by commit 812711ce "Implement
__raw_{read,write}[bwl] on all architectures".

git show 812711ce:include/linux/compiler.h
fatal: Path 'include/linux/compiler.h' exists on disk, but not in '812711ce'.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

u-boot's byteorder headers did not contain endianness attributions
for use with sparse, causing a lot of false positives.  Import the
kernel's latest definitions, and enable them by including compiler.h
and types.h.  They come with 'const' added for some swab functions, so
fix those up, too:

include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default]

Also, note: u-boot's historic __BYTE_ORDER definition has been
preserved (for the time being at least).

We also remove ad-hoc barrier() definitions, since we're including
compiler.h in files that hadn't in the past:

macb.c:54:0: warning: "barrier" redefined [enabled by default]

In addition, including compiler.h in byteorder changes the 'noinline'
definition to expand to __attribute__((noinline)).  This fixes
arch/powerpc/lib/bootm.c:

bootm.c:329:16: error: attribute '__attribute__': unknown attribute
bootm.c:329:16: error: expected ')' before '__attribute__'
bootm.c:329:25: error: expected identifier or '(' before ')' token

powerpc sparse builds yield:

include/common.h:356:22: error: marked inline, but without a definition

the unknown-reason inlining without a definition is considered obsolete
given it was part of the 2002 initial commit, and no arm version was
'fixed.'

also fixed:
ydirectenv.h:60:0: warning: "inline" redefined [enabled by default]

and:

Configuring for devconcenter - Board: intip, Options: DEVCONCENTER
make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1
make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2
powerpc-fsl-linux-size: './u-boot': No such file
4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration':
include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available
4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here

and:

In file included from crc32.c:50:0:
crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration]
crc32table.h:4:1: error: initializer element is not constant
crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]')

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
[trini: Remove '#endif' in include/common.h around setenv portion]
Signed-off-by: Tom Rini <trini@ti.com>

These boards have long reached EOL, and there has been no indication
of any active users of such hardware for years.  Get rid of the dead
weight.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@denx.de>

This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

Introduce a new configuration token CONFIG_MPC830x to be shared among
mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor
existing common code so to make future introduction of 8309 simpler.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
for qe variables
with #if defined(CONFIG_QE)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

The timeout_save variable was only used by the DDR111_134
erratum code. It was being set, but never used. Newer compilers
will actually complain about this.

Signed-off-by: Andy Fleming <afleming@freescale.com>

Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.

So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel
driver can use it to calculate the shaper prescaler and rate.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the
total portal number, buffer pool number etc, we can use this info to limit
those resources in kernel driver.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

R6 was in ePAPR draft version but was dropped in official spec.
Removing it to comply.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Since empty DIMM slot is allowed on other than the first slot, remove the
error message if SPD is not found in this case.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.

Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.

For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.

Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.

Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.

It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
	000 -> Termsel off
	001 -> 120 Ohm
	010 -> 180 Ohm
	011 -> 75 Ohm
	100 -> 110 Ohm
	101 -> 60 Ohm
	110 -> 70 Ohm
	111 -> 47 Ohm

Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.

Extend DDR register timing_cfg_1 to have 4 bits for each field.

DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
    clusters-each core runs up to 1.2 GHz, with an architecture highly
    optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
    cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
    each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
    including Turbo or Viterbi decoding, Turbo encoding and rate matching,
    MIMO MMSE equalization scheme, matrix operations, CRC insertion and
    check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
    and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
    the e6500 cores, SC3900 FVP cores, memories and external interfaces.
    CoreNet fabric interconnect runs at 667 MHz and supports coherent and
    non-coherent out of order transactions with prioritization and
    bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
  Frame Manager (FMan), which supports in-line packet parsing and general
    classification to enable policing and QoS-based packet distribution
  Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
    of queue management, task management, load distribution, flow ordering,
    buffer management, and allocation tasks from the cores
  Security engine (SEC 5.3)-crypto-acceleration for protocols such as
    IPsec, SSL, and 802.16
  RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
    outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
    bandwidth saving and high utilization of processor elements. The
    9856-Kbyte internal memory space includes the following:
  32 Kbyte L1 ICache per e6500/SC3900 core
  32 Kbyte L1 DCache per e6500/SC3900 core
  2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  2048 Kbyte unified L2 cache for the e6500 cluster
  Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
  Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
    of up to 8 lanes
  Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
    less antenna connection
  Two 10-Gbit Ethernet controllers (10GEC)
  Six 1G/2.5-Gbit Ethernet controllers for network communications
  PCI Express controller
  Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

The T4 has added devices to previous corenet implementations:

* SEC has 3 more DECO units
* New PMAN device
* New DCE device

This doesn't add full support for the new devices. Just some
preliminary support.

Move PMAN LIODN to upper half of register

Despite having only one LIODN, the PMAN LIODN is stored in the
upper half of the register. Re-use the 2-LIODN code and just
set the LIODN as if the second one is 0. This results in the
actual LIODN being written to the upper half of the register.

Signed-off-by: Andy Fleming <afleming@freescale.com>

Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Create new files to handle 2nd generation Chassis as the registers are
organized differently.

 - Add SerDes protocol parsing and detection
 - Add support of 4 SerDes
 - Add CPRI protocol in fsl_serdes.h
	The Common Public Radio Interface (CPRI) is publicly available
	specification that standardizes the protocol interface between the
	radio equipment control (REC) and the radio equipment (RE) in wireless
	basestations. This allows interoperability of equipment from different
	vendors,and preserves the software investment made by wireless service
	providers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Corenet 2nd generation Chassis has different RCW and registers for SerDes.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

The QCSP registers are expanded and moved from offset 0 to offset 0x1000
for SoCs with QMan v3.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Expand the reference clock select to three bits
000: 100 MHz
001: 125 MHz
010: 156.25MHz
011: 150 MHz
100: 161.1328125 MHz
All others reserved

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each cluster has up to
4 cores sharing same clock, which can be chosen from one of three PLLs in
the cluster group with one of the devisors /1, /2 or /4. Two clusters are
put together as a cluster group. These two clusters share the PLLs but may
have different divisor. For example, core 0~3 are in cluster 1. Core 4~7
are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2
are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group
A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.

PME and FMan blocks can take different PLLs, configured by RCW.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Panic if the number of cores is more than CONFIG_MAX_CPUS because it will
surely overflow gd structure.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>

These assembly macros simplify codes to add and delete temporary TLB entries.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>