Align device tree with the last kernel 5.10. Add some
compatible changes and pin control modifications.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I03be4704463750227a220b256f386687f0eec058
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/188174


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

This patch adds changes to support the secure secret
provisioning (SSP).

Add a specific platform build that constructs a dedicated BL2
image to support the SSP feature.
Supported boot mode is limited to serial boot (USB or UART).

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I85de08efd8d4183cd7e1bc0b6f17d247669b82ce
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/185336


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Enable watchdog secure interrupt to dump registers in case
of non secure watchdog.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Icc9c32125af389df01215687ca915ea67023cda3
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/186542


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Add new defines and update the firmware configuration file
to use directly that defines. It will allow to directly
reflect BL32 size update during build.

Change-Id: Ieb11c9e0bac155d26fda9d0f3b086c55d5ce4783
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/186539


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Ordering between read and write transactions should be disabled on each
port.
The DDR controller ensures that all read/write commands from the
application port interface are transported to the DFI interface in the
order of appearance.

Change-Id: I70c16cfe6c8ae2587d1131c3e7ddf183d20a3bb7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184352


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Lionel DEBIEVE <lionel.debieve@st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Tested-by: Yann GAUTIER <yann.gautier@st.com>

Invert position of BL32 and BL32_DT in memory, otherwise the BL32
BSS initialization overwrote DT area. With this inversion BL32 BSS
overwrite a no more used memory area.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Change-Id: I0a8cd0c64921d2813be4b31212510f53caea9158
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184834


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

Add the trusted boot firmware configuration information into
the BL2 device tree. It enabled the authentication.
MBEDTLS heap is not defined, it will use the hard coded one.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Change-Id: I47181d179b814dc512dc527ae54a5a19a126f1c5
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184833


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

vdd_usb must not be present unless vdda1v8 is present. So, as vdda1v8 is
disabled during standby, vdd_usb cannot be kept on during suspend.

Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Change-Id: I49d9683fd2ca7f89cf17cc3147585fc6b8916388

STM32MP_USE_STM32IMAGE is now used to distinguished the 2 possible
configurations.
If STM32MP_USE_STM32IMAGE is set, the legacy loading scheme is used. It
implies a single binary containing BL2, BL32 and a shared device tree
blob in case sp_min is used. The legacy loading scheme can also manage
the loading of OP-TEE.
If STM32MP_USE_STM32IMAGE is not set, then FIP is used, and it implies
FCONF as well.

Change-Id: Ibf93982e6be2f551d65094c985eaf5a6bd2ab788
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Add the corresponding firewall memory regions
into device tree.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Ie39b0339f3c42b3dd756354138a872500c64f84c

Add the UUID into the io policies node that are retrieved
by BL2 using stm32mp_fconf_io.c populate function.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I595d5a41a1e0a27fcc02ea2ab5495d9dbf0e6773
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/178509


Reviewed-by: Yann GAUTIER <yann.gautier@st.com>
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>

A new flag STM32MP_DDR_DUAL_AXI_PORT is added, and enabled by default.
It will allow choosing single or dual AXI ports for DDR.

Change-Id: I48826a66a6f4d18df87e081c0960af89ddda1b9d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Change-Id: I56d12ae9347e5b67cff2cfd0dff3f365f82316a6

Change-Id: Iedaf0f7058249a1e30610de8366e422c70f3b2c2

Change-Id: I544654eadfb9bac86683c191ea69299612c8ec51
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Add FW_CONFIG device tree files for all boards. The file content is for
the moment common to all boards. It describes where the different images
will be loaded.

Change-Id: Id957b49b0117864136250bfc416664f815043ada
Signed-off-by: Yann Gautier <yann.gautier@st.com>

BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP file.
One DTB is created for each BL. To reduce their sizes, 2 new dtsi file are
in charge of removing useless nodes for a given BL. This is done because
BL2 and BL32 share the same device tree files base.

Change-Id: I1ffada0af58486d4cf6044511b51e56b52269817
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Change-Id: I0adb2c6bf21e840d6b795292357f3615361b767e
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Enable TRUSTED_BOARD_BOOT. This change removes calls to
stm32mp_check_header() and stm32mp_auth_image() when boot images
are loaded since images are now verified from the authentication
framework.

Change-Id: Iec5b645e1581543c99ae59bdb4dd033c577f2295
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

Change platform DTS and shared resources driver to ensure all
secureable peripherals of ETZPC is configured so that we can
check each configuration against resources assignation.

Change-Id: I66b75e990e1d3ba65aea6051811568fb2e5b02e2
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/153126


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

This parameter "st,phy-cal" becomes optional and when it is
absent the built-in PHY calibration is done.

It is the case in the helper dtsi file "stm32mp15-ddr.dtsi"
except if DDR_PHY_CAL_SKIP is defined.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I38ffd4aeca88fd45819d4e7d20840465a8a8e9bf
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/151296


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

PLL1 settings are now computed from OPP table frequencies.

Change-Id: Icc8ab3975cb5e1ef4ab14796868735d39d2e5d65
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Fix the following DT dtc warnings for stm32mp1 boards:

Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@0:
 node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@1:
 node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@2:
 node has a unit name, but no reg property
Warning (unit_address_vs_reg): /soc/rcc@50000000/st,pll@3:
 node has a unit name, but no reg property

Update device tree bindings documentation.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I91be408ea1d9b0474caf4965175df33792b7e11e

Align STPMIC1 configuration with linux.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I4efaa889fec4337ab2516daf17452f63f874a757
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/144883


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

No more used, "st,non-secure-otp" property replaces them.

Change-Id: Iacf3b547951e17503ba826b537c7deaf8a53dcd4
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

Avoid mixing dash and underscore.

Change-Id: I7f8b6c5397d789c3cb2fdbae50205610c5595af7
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Originally required for CubeMX.
Still the case?

Change-Id: Icab89afbdb4852821062fa00ffadc07aba39aea9

Change-Id: I81ceb6399e2f6067be42afc5192f00a497a399d9

Change-Id: I3511c88d174c7404da20910526427d096fce9241
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

Change-Id: I8e0ba794e5ded1290fb83fe8d43ce54d4dc0e320
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Set non-secure property on platform secure OTP nodes that non-secure world
is allowed to access through secure world services.
These are the SoC MAC address and the ST boards board_id OTPs.

Change-Id: Idfa6322d9d5c35285706d0b2d32ae09af38684a7
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/138264


Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
Reviewed-by: CIBUILD <smet-aci-builds@lists.codex.cro.st.com>
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list allows easy access to OTP offsets defined in BSEC node,
where more OTP definitions with offsets in bytes and length have
been added (replace hard-coded values).
Each board may redefine this list, especially for board_id info.

Change-Id: I910ae671b3bf3320ee6500fecc9ec335ae67bbda
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts

Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>

Without this node, the board fails to boot and panics in the function
stm32mp_init_auth().

Change-Id: Ia54924410dac2a8c94dd6e45d7e93977fe7d87e2
Signed-off-by: Yann Gautier <yann.gautier@st.com>

FMC node bindings are modified to add EBI controller node.
FMC driver and associated device tree files are modified
to support these new bindings.

Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

enable virtio-rng component for morello fvp platform

Change-Id: I89b950f067a4d14dfa418de3859c88c8f91cf7c5
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>

The FPGA images used in Arm Ltd. focus on CPU cores, so they share a
common platform, with a minimal set of peripherals (interconnect, GIC,
UART).
This allows to support most platforms with a single devicetree file.
The topology and number of CPU cores differ, but those will added at
runtime, in BL31. Other adjustments (GICR size, SPE node, command line)
are also done at this point.

Add the common devicetree file to TF-A's build system, so it can be
build together with BL31. At runtime, the resulting .dtb file should be
uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time.

Change-Id: I3206d6131059502ec96896e95329865452c9d83e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Change-Id: Ib5945c37983505f327a195bdb8b91ed1b7b90921
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

There is one dtsi file per SoC version:
- STM32MP151: common part for all version, Single Cortex-A7
- STM32MP153: Dual Cortex-A7
- STM32MP157: + GPU and DSI, but not needed for TF-A

The STM32MP15xC include a cryptography peripheral, add it in a dedicated
file.

There are 4 packages available, for which  the IOs number change. Have one
file for each package. The 2 packages AB and AD are added.

STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common
dkx file is then created.

Some reordering is done in other files, and realign with kernel DT files.

The DDR files are generated with our internal tool, no changes in the
registers values.

Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1
Signed-off-by: Yann Gautier <yann.gautier@st.com>

This is as part of the architecture change in TC0.

Change-Id: I470241f67938e7998941d26f0e8bc05073234152
Signed-off-by: Usama Arif <usama.arif@arm.com>