- Mar 26, 2008
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Dave Liu authored
original ata_piix driver is using IDE framework, not real SATA framework. For now, the ata_piix driver is only used by x86 sc520_cdp board. This patch makes the ata_piix driver use the new SATA framework, so - remove the duplicated command stuff - remove the CONFIG_CMD_IDE define in the sc520_cdp.h - add the CONFIG_CMD_SATA define to sc520_cdp.h Signed-off-by:
Dave Liu <daveliu@freescale.com>
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Dave Liu authored
move the cmd_sata.c from common/ to drivers/ata_piix.c, the cmd_sata.c have some part of ata_piix controller drivers. consolidate the driver to have better framework. Signed-off-by:
Dave Liu <daveliu@freescale.com>
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Jon Loeliger authored
Each file that can be built here now follows some CONFIG_ option so that they are appropriately built or not, as needed. And CONFIG_ defines were added to various board config files to make sure that happens. The other board/freescale/*/Makefiles no longer need to reach up and over into ../common to build their individually needed files any more. Boards that are CDS specific were renamed with cds_ prefix. Signed-off-by:
Jon Loeliger <jdl@freescale.com>
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Kumar Gala authored
When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Anton Vorontsov authored
Linux understands "host" (default), "peripheral" and "otg" (broken). Though, U-Boot doesn't restrict dr_mode variable to these values (think of renames in future). Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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Joe D'Abbraccio authored
With the original value of 1/2 clock cycle delay, the system ran relatively stable except when we run benchmarks that are intensive users of memory. When I run samba connected disk with a HDBENCH test, the system locks-up or reboots sporadically. Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
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Scott Wood authored
The device trees for these boards describe PCI I/O as starting from address zero from the device's perspective. Placing I/O elsewhere may cause problems with certain PCI boards, and may cause problems with Linux. Signed-off-by:
Scott Wood <scottwood@freescale.com>
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Anton Vorontsov authored
At least on the "33MHz Pilot" board crystal is actually 33.3MHz. This patch fixes "system time drifting" problem. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com>
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Anton Vorontsov authored
This is needed to update /choosen/linux,stdout-path properly. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com>
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Anton Vorontsov authored
Plus modify environment to use it and remove bootfile env variable, it is internal and CONFIG_BOOTFILE is used for these purposes. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com>
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Anton Vorontsov authored
Current DDR setup easily causes memory corruption, this patch fixes it. Also fix TIMING_CFG0_MRS_CYC definition. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com>
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Anton Vorontsov authored
Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com>
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Anton Vorontsov authored
This is needed for BCM PHYs to work on this board. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com>
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Anton Vorontsov authored
This is primarily for the early console support. Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com>
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Anton Vorontsov authored
On the MPC8377ERDB: 2 SATA and 2 PCI-E. On the MPC8378ERDB: 2 PCI-E On the MPC8379ERDB: 4 SATA Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com>
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Anton Vorontsov authored
Signed-off-by:
Anton Vorontsov <avorontsov@ru.mvista.com>
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Jerry Van Baren authored
Signed-off-by:
Gerald Van Baren <vanbaren@cideas.com> Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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Michael Barkowski authored
There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM. Signed-off-by:
Michael Barkowski <michael.barkowski@freescale.com> Acked-by:
Kim Phillips <kim.phillips@freescale.com>
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Michael Barkowski authored
The following changes are based on kernel UCC ethernet performance: 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT switch to enable this setting. The following changes are based on the App Note AN3369 and verified to improve memory latency using LMbench: 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting previously. 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on Twr=15ns, and this was already the setting in DDR_MODE) 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on Trp=15ns) 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on Tras=40ns) 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on Trcd=15ns) 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on Trfc=75ns) 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based on Tfaw=50ns) 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based on CL=3 and WL=2). Signed-off-by:
Michael Barkowski <michael.barkowski@freescale.com> Acked-by:
Kim Phillips <kim.phillips@freescale.com>
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Michael Barkowski authored
Use available shift/mask macros to define DDR configuration. Signed-off-by:
Michael Barkowski <michael.barkowski@freescale.com> Acked-by:
Kim Phillips <kim.phillips@freescale.com>
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Timur Tabi authored
Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET. Cleaned up the board header files to make selecting the VSC7385 easier to control. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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- Mar 25, 2008
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Jerry Van Baren authored
These defines embedded the u-boot env variables and/or the bd_t structure in the fdt blob. The conclusion of discussion on the u-boot email list was that embedding these in the fdt blob is not useful: there are better ways of passing the data (in fact, the fdt blob itself replaces the bd_t struct). The only board that enables these is the stxxtc and they don't appear to be used by linux. Signed-off-by:
Gerald Van Baren <vanbaren@cideas.com> Acked-by:
Kim Phillips <kim.phillips@freescale.com>
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Bryan O'Donoghue authored
Signed-off-by:
Bryan O'Donoghue <bodonoghue@codehermit.ie>
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- Mar 20, 2008
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Bartlomiej Sieka authored
Signed-off-by:
Bartlomiej Sieka <tur@semihalf.com>
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- Mar 19, 2008
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Martin Krause authored
- insert partition for dtb blob to TQM5200B MTD layout - set env variables dependent on the configured board (TQM5200 or TQM5200B) Signed-off-by:
Martin Krause <martin.krause@tqs.de>
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- Mar 18, 2008
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Yuri Tikhonov authored
The patch introduces the alternative configuration of the log buffer for the lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., PPC440EPX_GPT0_COMP5). To enable this, alternative, configuration the U-Boot board configuration file for lwmon5 includes the definitions of alternative addresses for header (CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR). The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set, and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h). Signed-off-by:
Yuri Tikhonov <yur@emcraft.com>
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Yuri Tikhonov authored
Signed-off-by:
Dmitry Rakhchev <rda@emcraft.com> Signed-off-by:
Yuri Tikhonov <yur@emcraft.com>
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Yuri Tikhonov authored
* External Watchdog test; * dsPIC tests; * FPGA test; * GDC test; * Sysmon tests. Signed-off-by:
Dmitry Rakhchev <rda@emcraft.com> Signed-off-by:
Yuri Tikhonov <yur@emcraft.com>
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- Mar 16, 2008
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Mike Frysinger authored
The parallel flash on the BF537-STAMP is CFI compliant, so there is no need for the board specific driver at all. Just use the common CFI driver. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Stop tying things to the processor that should be tied to other defines and change BFIN_CPU to CONFIG_BFIN_CPU so that it can be used in the build system to select the -mcpu option. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Heiko Schocher authored
Fix configuration for mgcoge board Signed-off-by:
Heiko Schocher <hs@denx.de>
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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- Mar 15, 2008
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Stefan Roese authored
This patch adds USB OHCI support to the Canyonlands board port. It also enables EXT2 support. Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by:
Stefan Roese <sr@denx.de>
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Stefan Roese authored
This patch adds support for the AMCC Canyonlands 460EX evaluation board. Signed-off-by:
Stefan Roese <sr@denx.de>
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Niklaus Giger authored
Signed-off-by:
Niklaus Giger <niklaus.giger@netstal.com>
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Niklaus Giger authored
Cleanup: Remove custom flash driver for 8 bit boot-eprom and replace it with the FLASH_CFI_LEGACY et al. config options. Signed-off-by:
Niklaus Giger <niklaus.giger@netstal.com>
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- Mar 08, 2008
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Heiko Schocher authored
initialize the UPIOx controller. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
add support for the config Flash. initialize the UPIOx controller. Signed-off-by:
Heiko Schocher <hs@denx.de>
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- Mar 07, 2008
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Kim Phillips authored
the dts file basenames were updated in linux - this helps avoid inadvertently loading any old dtbs laying around. Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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