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Alexander Arndt
aarndt
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Andreas Findeklee afindeklee
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Annette Kobou akobou
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Armin Mück amueck
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Daniel Ehrler dehrler
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Devran Ölcer doelcer
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Dieter Scheufele dscheufele
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Dietmar Kolbus dkolbus
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Dominik Wurster Wurster
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Eberhard Stoll estoll
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Florian Mayer fmayer
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Frieder Schrempf
fschrempf
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Julian Bauknecht jbauknecht
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Jó Bitsch jbitsch
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Jürgen Kling
jgkling
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Klemenz Christof kchristof
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Lukas Loosli lloosli
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Marc Gonser mgonser
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Markus Abegg mabegg
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Maximilian Adducchio Maximilian
- Feb 11, 2021
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Ludovic Barre authored
This patch allows to execute bl33 in hypervisor mode if BL33_HYP compilation flag is defined. Change-Id: Icd0de8e9a8180f2ca67952bd6b98f38712e52716 Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Sebastien Pasdeloup <sebastien.pasdeloup-ext@st.com> Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/187471 Reviewed-by:
CITOOLS <smet-aci-reviews@lists.codex.cro.st.com> Reviewed-by:
CIBUILD <smet-aci-builds@lists.codex.cro.st.com> Reviewed-by:
Yann GAUTIER <yann.gautier@st.com> Tested-by:
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Lionel Debieve authored
This patch adds changes to support the secure secret provisioning (SSP). Add a specific platform build that constructs a dedicated BL2 image to support the SSP feature. Supported boot mode is limited to serial boot (USB or UART). Signed-off-by:
Lionel Debieve <lionel.debieve@st.com> Change-Id: I85de08efd8d4183cd7e1bc0b6f17d247669b82ce Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/185336 Reviewed-by:
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Lionel Debieve authored
Rather that a CPU reset, tamper must call the system reset to restart from a clean environment. Signed-off-by:
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Lionel Debieve authored
Enable watchdog secure interrupt to dump registers in case of non secure watchdog. Signed-off-by:
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Lionel Debieve authored
Rework the early interrupt to dump core registers in debug mode. In release mode, it will clear the interrupt and wait watchdog to expire. Signed-off-by:
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Lionel Debieve authored
This function can be used to dump core registers when an issue occurred. It will be automatically called in debug mode and print information. It uses a first core boolean to avoid unexpected dump information on a SGI1 irq request also used for a standard core hotplug. Signed-off-by:
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Lionel Debieve authored
Do not build firmware configuration file if no AARCH32_SP is selected. It will avoid build issue when building only bl2 target. Signed-off-by:
Nicolas TOROMANOFF <nicolas.toromanoff@st.com> Reviewed-by:
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Lionel Debieve authored
Add new defines and update the firmware configuration file to use directly that defines. It will allow to directly reflect BL32 size update during build. Change-Id: Ieb11c9e0bac155d26fda9d0f3b086c55d5ce4783 Signed-off-by:
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Lionel Debieve authored
Add STM32CubeProgrammer communication update for SSP support. Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com> Change-Id: I1830bff82d87b3535f0787eb5f47c56960feccaa Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/185335 Reviewed-by:
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Lionel Debieve authored
Add function to find from device tree the proper regulator that controls the VDD domain. Rework the dt_get_cpu_regulator_name to use the same generic function. Signed-off-by:
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Lionel Debieve authored
In case of SEPARATE_CODE_AND_RODATA defined, the linker will use the BL2_RO and BL2_RW defined. Signed-off-by:
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Nicolas Le Bayon authored
Ordering between read and write transactions should be disabled on each port. The DDR controller ensures that all read/write commands from the application port interface are transported to the DFI interface in the order of appearance. Change-Id: I70c16cfe6c8ae2587d1131c3e7ddf183d20a3bb7 Signed-off-by:
Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/184352 Reviewed-by:
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Lionel Debieve authored
STM32 board with a FIP image can have same trusted boot as STM32 image. Signed-off-by:
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Lionel Debieve authored
Reserved memory must be filled depending the architecture. This patch automatically detect the address and size length to adapt the address-cells and size-cells values. Signed-off-by:
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Yann Gautier authored
When going to low-power modes, the IO compensation is disabled through the function stm32mp1_syscfg_disable_io_compensation(). But at this step, the SYSCFG clock could be disabled. Enable it at the beginning of the sequence. Change-Id: I9e805cf5ca232f702963925a7d0d7d107dbb874d Signed-off-by:
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Nicolas Toromanoff authored
Use a more flexible and easier to extend definition of the MAX_PLAT_TABLES value. Signed-off-by:
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Lionel Debieve authored
Fix MISRA issues and invert the spi_nor_ready status to improve readability. Signed-off-by:
Christophe KERELLO <christophe.kerello@st.com> Reviewed-by:
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Lionel Debieve authored
Invert test logic on the status register control to fix issue when the bit SR_QUAD_EN_MX is not set. Signed-off-by:
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Yann Gautier authored
Add -Wsign-compare to TF_CFLAGS to check signedness comparison during STM32MP1 platform compilation. Change-Id: I4cada49622f44258d3e0da4560a566de9c7d54b3 Signed-off-by:
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Yann Gautier authored
Add casts where required to avoid compialtion error when enabling Wsign-compare. Change-Id: Ie4c9c0c935d39ff9a2165b909172aacb3e94ab4d Signed-off-by:
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Yann Gautier authored
Avoid compilation errors: "comparison of integer expressions of different signedness" by changing type of num to uint32_t. And force cast where required. Change-Id: I891e4a288a964ffdb52129813ba8652c5bcf85b2 Signed-off-by:
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Gabriel Fernandez authored
Implement dedicated platform function plat_scmi_clock_set_rate(), to override the weak defined function. Change-Id: I651e3060588196baa52cf8d80f1ad9af528cf142 Signed-off-by:
Gabriel Fernandez <gabriel.fernandez@st.com> Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/185719 Reviewed-by:
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Gabriel Fernandez authored
Remove rate description by arrays as Linux kernel does not properly handle rate arrays. Change-Id: I1ee37b8f5e3f10a03dee9f2ed3c699777840e3e9 Signed-off-by:
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Gabriel Fernandez authored
All clocks are exposed as single rate clocks. Concerning MPU clock, only CPU OPP can act and only valid rates are expected for this very clock. Change-Id: I2f76135996da23dae590aa9d77e3bfd6c03a68c1 Signed-off-by:
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Nicolas Toromanoff authored
A platform specific mebedtls_config.h can now be defined if needed by the parent makefile. Signed-off-by:
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Nicolas Toromanoff authored
Public key brainpool ecdsa DER certificate are 92 byte long: OID for brainpool curve are 1 byte bigger than the one for NIST curve. Signed-off-by:
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Nicolas Toromanoff authored
with platform format PK In some platform the digest of the public key saved in the OTP is not the the digest of the exact same public key buffer needed to check the signature. Typically, check signature may need a BER encapsulated public key, but the hash saved in OTP may be the hash of the plain public key. Add a new platform weak function to transform the public key buffer used by verify_signature to a buffer which hash is saved in OTP. Signed-off-by:
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Nicolas Toromanoff authored
Updated cert_tool to be able to select brainpool P256t1 or NIST prim256v1 curve for certificates signature. Signed-off-by:
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Nicolas Toromanoff authored
Invert position of BL32 and BL32_DT in memory, otherwise the BL32 BSS initialization overwrote DT area. With this inversion BL32 BSS overwrite a no more used memory area. Signed-off-by:
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Lionel Debieve authored
Add the trusted boot firmware configuration information into the BL2 device tree. It enabled the authentication. MBEDTLS heap is not defined, it will use the hard coded one. Signed-off-by:
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Lionel Debieve authored
Move the fw_config authentication structure into the common part. Without BL1, the fw_config will be added into the BL2 firmware. It will be loaded from FIP and authenticated in BL2. Signed-off-by:
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Lionel Debieve authored
Call the stm32mp_system_reset from the driver for the PSCI ops. Signed-off-by:
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Lionel Debieve authored
Add the system reset management into the stm32mp reset driver. Signed-off-by:
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Lionel Debieve authored
TZC400 configuration is applied at the end of BL2 after MMU and data cache being turned off. Configuration needs to retrieve the DDR size to generate the correct region. Access to the size fails because the value is still in the data cache. Flushing the size is mandatory. Signed-off-by:
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Pascal Paillet authored
Move PWR related init from bl2 to bl32. Change-Id: I61b62ef2208bee0e502dd5fab277d806c205e7b1 Signed-off-by:
Pascal Paillet <p.paillet@st.com> Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/tf-a/+/183647 Reviewed-by:
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Yann Gautier authored
The flush of the BL33 image is already handled in load_image(). For ED1/EV1 boards, this extra flush was also doing nothing, as for those boards image_base + image_max_size = 0x100000000, which overflows an u32, and 0 was used. This flush is now replaced with a correct invalidation of the cache directly in io_stm32image. Change-Id: Ibe301e017669b10d8c321abef27c674c914e43b6 Signed-off-by:
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Yann Gautier authored
When retrieving data from stm32 image file, the header is removed with a memcpy that shifts the data to overwrite the useless header for next binary. STM32 binary from boot device: |-------------------------------------| | header | payload | |-------------------------------------| After the memcpy: |-------------------------------------| | payload | remain | |-------------------------------------| But the remaining data after the shifted payload is still in the cache. As it is of no use for anyone, just invalidate the cache at this address. Change-Id: Ice2af3b1ca49eccb79bfc62db60437e259d344ca Signed-off-by:
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Yann Gautier authored
The boot device is now checked inside a dedicated rule, that is only called during BL2 compilation step Change-Id: Ie7bcd1f166285224b0c042238989a82f7b6105c6 Signed-off-by:
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Lionel Debieve authored
In case of programmer load, we must invalidate cache used for the download buffer. Signed-off-by:
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Yann Gautier authored
When returning from STANDBY state, only checking the boot action status is not enough. We also have to check the non-secure return address is correct, and the saved context is OK in backup RAM. This is required for STANDBY with DDR off, which can be used when a user issues a shutdown. Change-Id: I4b1d5159cd7a524eb893229ea9bcf628746de0ab Signed-off-by:
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